GAA Gate Stack Blocking Layer for Void-Sealed Replacement Gates

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Solution Overview

Problem

The integration of gate-all-around (GAA) semiconductor devices faces challenges in void formation during the replacement gate process due to shrinking dimensions and limited gap filling capability, leading to impurity introduction and transistor performance degradation.

Innovation Solution

A blocking layer is formed above the work function metal layer to seal voids and prevent impurity entry, enhancing adhesion with the metal fill layer, thereby improving transistor performance by stabilizing work function metal resistance and threshold voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the replacement gate process is used to fabricate GAA devices, then gate control is improved, but voids form during the process leading to impurity introduction and performance degradation

Engineering Contradiction:
Improvegate controlVSAvoidimpurity introduction
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A blocking layer is formed over the work function metal layer before the metal fill layer deposition to preemptively prevent impurity entry into voids. This preliminary protective action ensures that even if voids form during the replacement gate process, impurities cannot contaminate the work function metal layer, thus maintaining device reliability and performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blocking layer acts as an intermediary barrier between the work function metal layer and the external environment. This intermediate layer prevents direct contact between impurities and the work function metal, resolving the contradiction by introducing a protective mediator that allows the replacement gate process to proceed while blocking harmful impurity introduction

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If transistor dimensions are scaled down to sub-10 nm nodes, then production efficiency is improved, but void formation becomes more severe due to limited gap filling capability

Engineering Contradiction:
Improveproduction efficiencyVSAvoidvoid formation control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The blocking layer is deposited in advance before metal fill layer formation to preemptively seal voids. This preliminary action addresses the manufacturing precision issue by ensuring voids are sealed before impurity introduction, allowing continued scaling to sub-10 nm nodes while maintaining production efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blocking layer serves as an intermediary protective barrier that decouples the void formation issue from impurity introduction. This allows the manufacturing process to continue at scaled dimensions with high productivity while the blocking layer mediates the precision issue by preventing void-related defects

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If a blocking layer is formed to seal voids, then impurity introduction is prevented, but additional fabrication steps are required

Engineering Contradiction:
Improveimpurity preventionVSAvoidfabrication process complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The blocking layer is formed using standard atomic layer deposition (ALD) processes that are already part of the existing fabrication toolkit. This multi-functional approach uses an existing process capability to achieve the new function of void sealing, minimizing the increase in fabrication complexity while effectively preventing impurity introduction

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250359171A1Multi-Gate Semiconductor Device And Fabrication Method Thereof
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250359171A1 patent drawing
  • US20250359171A1 patent drawing
  • US20250359171A1 patent drawing

AI summary

A semiconductor device include nanostructures vertically stacked over a substrate, a gate stack wrapping around at least one of the nanostructures, a source/drain (S/D) epitaxial feature abutting the nanostructures, an insulating layer interposing the S/D epitaxial feature and the gate stack, and gate spacers disposed on sidewalls of the gate stack. The gate stack includes a first metal layer, a second metal layer, a blocking layer sandwiched by the first metal layer and the second metal layer, and voids stacked between the first metal layer and the blocking layer. The first metal layer is below a top surface of the gate spacers.