GAA FET Gate Stack Dielectric Profiling for Multi-Vt Reliability
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Solution Overview
Problem
Conventional gate stack channels in gate-all-around field-effect transistors face challenges in simultaneously achieving reliability anneal and multi-threshold voltage due to limited spacing, leading to issues like undesired variability and mobility loss.
Innovation Solution
The formation of dielectric material on interfacial layers is separated into two distinct deposition processes, allowing for reliability annealing and multi-Vt processing at a low thermal budget, using a modified high-k dielectric profile and laser anneal, which improves gate stack quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stack channels are used with limited spacing, then device integration is achieved, but reliability anneal and multi-threshold voltage cannot be simultaneously achieved
Solution Approach 1:
The patent segments the gate stack structure into multiple channels with different interfacial layer configurations. Specifically, different channels have different dielectric material thicknesses (first portion thickness vs second portion thickness), enabling each channel to have distinct threshold voltages while sharing the same gate electrode structure. This segmentation allows simultaneous achievement of reliability anneal and multi-Vt capability.
Solution Approach 2:
The patent applies local quality by creating spatial variation in dielectric material thickness around different channels. The first portion of dielectric material has a different thickness compared to the second portion, which locally modifies the electric field distribution and threshold voltage for channels positioned at different locations. This enables tailored threshold voltages for different channels while maintaining overall gate stack reliability.
2Manufacturing precision
If dielectric material is formed in a single deposition process, then process simplicity is maintained, but threshold voltage control precision is insufficient
Solution Approach 1:
The dielectric material formation is segmented into two separate deposition processes. The first deposition process forms a first portion of dielectric material with a first thickness, and the second deposition process forms a second portion with a second thickness. This segmentation enables precise control of threshold voltage by independently controlling the thickness of each dielectric portion, achieving superior Vt control despite increased process complexity.
3Reliability
If high thermal budget anneal is used, then reliability anneal is achieved, but interfacial layer regrowth occurs
Solution Approach 1:
The patent changes the thermal budget parameters of the anneal process by conducting it at a reduced temperature and for a limited duration. This modified anneal protocol provides sufficient reliability improvement while preventing excessive thermal energy that would cause interfacial layer regrowth. The parameter optimization balances reliability enhancement with interfacial layer stability.
Solution Approach 2:
The patent performs reliability anneal at a reduced thermal budget before final device completion. This preliminary anneal action improves gate stack reliability early in the process while preventing interfacial layer regrowth that would occur with higher temperature annealing later. The timing and temperature control prevent harmful regrowth while achieving reliability benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate stack reliability by preventing interfacial layer regrowth and improves negative-bias temperature instability and inversion-layer thickness, while achieving desired threshold voltage shifts.
Implementation Method 1
using a modified high-k dielectric profile and laser anneal
Implementation Method 2
performing an anneal process after forming the first metal oxide layer to achieve a threshold voltage (Vt) shift
Implementation Method 3
forming a first metal oxide layer on each of the first and second sacrificial layers
Data Source
AI summary
A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.