GAA Nanostructure Gate Stack for Selective Interfacial Layer Thickening

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Solution Overview

Problem

The challenge in manufacturing small GAA devices is filling high-k metal gates in the vertically shrinking space between channels, particularly in transistors requiring thicker interfacial layers for IO, ESD, and high voltage functions, which limits room for other layers and complicates achieving multiple threshold voltages.

Innovation Solution

An oxygen-scavenging capping layer is used to selectively thicken the interfacial gate dielectric layer through thermal treatment, allowing for the deposition of a work function metal layer while maintaining sufficient space, enabling the MPG process for multiple threshold voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the interfacial gate dielectric layer is thickened for IO, ESD, and high voltage transistors, then the reliability is improved, but the volume available for other layers is reduced

Engineering Contradiction:

Improvetransistor reliabilityVSAvoidvertical space between channels

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent applies different interfacial layer thicknesses to different transistor types within the same integrated circuit. IO, ESD, and high voltage transistors receive thickened interfacial layers for improved reliability, while core logic transistors maintain thinner layers to preserve vertical space. This is achieved through selective processing steps that target specific device regions, allowing each transistor type to have optimized dimensions for its specific function.

Inventive Principle:

Principle #3Local quality

2Productivity

If the vertical space between channels is reduced to improve scaling, then the productivity is improved, but the device complexity increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidmanufacturing process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the integrated circuit into different functional regions (core logic, IO, ESD, high voltage) and applies different fabrication sequences to each segment. This allows the manufacturing process to handle the complexity of varied interfacial layer thicknesses by treating each region independently, while still achieving high overall productivity through efficient process integration and selective processing steps.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If multiple threshold voltages are achieved through different interfacial layer thicknesses, then the adaptability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:

Improvemultiple threshold voltagesVSAvoidinterfacial layer thickness control

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary actions during the fabrication sequence to prepare for subsequent thickness differentiation. This includes forming initial interfacial layers with standard thickness, then applying selective thickening steps only to regions requiring IO, ESD, or high voltage functionality. The preliminary uniform layer provides a consistent base, while subsequent selective processing achieves the required thickness variations with controlled precision.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for finely tuned interfacial gate dielectric layers, maintains channel-to-channel spacing, and enables the achievement of multiple threshold voltages in integrated circuits, simplifying the manufacturing process and improving device performance.

Implementation Method 1

An oxygen-scavenging capping layer is used to selectively thicken the interfacial gate dielectric layer through thermal treatment

Methodology Applied

Scientific EffectOxygen scavenging: Absorption (physical)

Implementation Method 2

selectively thicken the interfacial gate dielectric layer through thermal treatment

Methodology Applied

Scientific EffectThermal treatment: Heating

Data Source

PatentUS12040191B2Semiconductor structures and methods thereof

Publication Date: 2024.07.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.