GAA Gate Stack Structure for Ultra-Low Threshold FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving ultra-low threshold voltages in field-effect transistors (FETs) due to constraints in gate stack geometries and the difficulty of depositing thick work function metal layers as devices scale down, particularly in gate-all-around (GAA) FETs, which affects manufacturing complexity and cost-effectiveness.
Innovation Solution
The development of gate structures for FETs with Al-based n-type and substantially Al-free p-type gate stacks, incorporating n-type and p-type work function metal layers in physical contact with gate dielectric layers, and the use of metal growth inhibition layers to prevent contamination and oxidation, allowing for the formation of FETs with ultra-low threshold voltages on the same substrate with reduced gate stack thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick work function metal layers are deposited to achieve ultra-low threshold voltages, then the threshold voltage control is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The gate stack is segmented into multiple functional layers: gate dielectric layer, work function metal layer, and metal growth inhibition layer. This segmentation allows each layer to perform its specific function independently, enabling precise threshold voltage control through the work function metal layer thickness while the inhibition layer prevents manufacturing complexity by stopping unwanted metal growth.
Solution Approach 2:
The metal growth inhibition layer is deposited beforehand to prevent excessive metal growth during subsequent processing steps. This preliminary action ensures that the work function metal layer maintains the optimal thickness for ultra-low threshold voltage without requiring complex real-time monitoring and control during deposition.
2Manufacturing precision
If thick work function metal layers are deposited to achieve ultra-low threshold voltages, then the threshold voltage control is improved, but the deposition difficulty increases as devices scale down
Solution Approach 1:
The metal growth inhibition layer acts as an intermediary between the substrate and the work function metal layer. It provides a controlled interface that limits metal growth, making it easier to deposit the work function metal layer with precise thickness control even as device dimensions scale down to nanometer ranges where deposition control becomes increasingly difficult.
Solution Approach 2:
The inhibition layer provides localized control over metal growth at the gate stack interface. By creating a region with different growth characteristics than the bulk substrate, it enables precise control of work function metal layer thickness in the critical area where threshold voltage control is needed, without affecting other areas of the device.
3Ease of manufacture
If traditional gate stack geometries are used, then manufacturing processes are simpler, but ultra-low threshold voltages cannot be achieved
Solution Approach 1:
The gate stack uses a composite structure combining gate dielectric material, work function metal material, and metal growth inhibition material. This composite approach allows the integration of multiple functionalities: electrical insulation from the dielectric, threshold voltage control from the work function metal, and growth control from the inhibition layer, achieving ultra-low threshold voltages while maintaining manufacturing feasibility.
Solution Approach 2:
The gate stack structure nests multiple functional layers within each other: the work function metal layer is deposited on the gate dielectric layer, and the metal growth inhibition layer is deposited on top of the work function metal layer. This nested arrangement maximizes the functional density within the gate stack geometry, enabling ultra-low threshold voltage control without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FETs with ultra-low threshold voltages while reducing gate stack layer thickness by 50% to 75% compared to traditional methods, simplifying manufacturing and improving cost-effectiveness, and allows for the selective formation of n-type and p-type FETs on the same substrate with different work function values.
Implementation Method 1
the use of metal growth inhibition layers to prevent contamination and oxidation
Data Source
AI summary
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.