GAA Gate Isolation Structure for Via Leakage Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges with current leakage between the gate structure and the via under the source/drain feature, which affects the performance and efficiency of the device.
Innovation Solution
The implementation of a cap layer under the gate structure in gate all around (GAA) transistor devices to prevent current leakage, using a method that involves forming a stacked structure of semiconductor layers with different lattice constants, patterning fin structures, and forming gate spacers and inner spacers to create a self-aligned gate structure that encircles the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure is formed over source/drain regions in conventional semiconductor devices, then the device achieves basic transistor functionality, but current leakage occurs between the gate structure and the via under the source/drain feature
Solution Approach 1:
An isolation layer is introduced as an intermediary structure between the gate structure and the via under the source/drain feature. This isolation layer acts as a mediator that prevents direct electrical contact and current leakage between these two conductive elements, solving the reliability issue without fundamentally changing the basic transistor architecture
Solution Approach 2:
The device structure is segmented into distinct functional regions with the isolation layer creating a clear separation between the gate structure and the via. This segmentation prevents unwanted electrical interaction while maintaining the individual functionality of each component, addressing the current leakage problem through structural division
2Productivity
If geometry size is reduced to increase functional density, then production efficiency improves and costs decrease, but current leakage problems between gate structure and via worsen
Solution Approach 1:
The isolation layer is formed in advance during the manufacturing process, before final via formation and gate structure completion. This preliminary action ensures that the isolation barrier is already in place to prevent current leakage, allowing the device to maintain reliability even as geometry sizes are reduced for higher productivity
3Reliability
If a cap layer is added under the gate structure to prevent current leakage, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The isolation layer formation process is merged with existing manufacturing steps in the device fabrication sequence. By integrating the isolation layer creation into the overall manufacturing flow rather than adding it as a completely separate process, the ease of manufacture is maintained while still achieving the reliability improvement through current leakage prevention
Data Source
AI summary
A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.