GAA Nanostructure Gate Wall for Lower Parasitic Capacitance
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around nanowires is challenging due to limitations in current fabrication methods, which affect gate control and device performance.
Innovation Solution
A method involving the formation of a wall structure between nanostructures to reduce parasitic capacitance, enhance device performance, and improve the process window for gate patterning, while maintaining the integrity of the gate structure and increasing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for GAA transistor features, then manufacturing process is simpler, but gate control and device performance deteriorate
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming sacrificial nanostructures, depositing first dielectric material, removing sacrificial structures, depositing second dielectric material, and selective removal. This segmentation allows precise control over gate-all-around formation while managing complexity through systematic process breakdown
Solution Approach 2:
Sacrificial nanostructures are formed in advance before the actual gate structure fabrication. These preliminary structures serve as templates that guide subsequent dielectric material deposition and define the final gate geometry, enabling precise gate control before the main fabrication sequence begins
2Productivity
If gate structure is tightly integrated around nanowires, then device density increases, but parasitic capacitance increases and process window narrows
Solution Approach 1:
Different dielectric materials are used in different spatial locations: first dielectric material fills gaps between nanostructures, while second dielectric material forms the gate structure. This local differentiation allows optimization of electrical properties in specific regions, reducing parasitic capacitance while maintaining high device density
Solution Approach 2:
The first dielectric material acts as an intermediary between the nanowire channels and the second dielectric material gate structure. This intermediate layer provides electrical isolation and control over the gate-nanowire interface, reducing parasitic capacitance effects while enabling tight integration
3Manufacturing precision
If aggressive patterning is used to increase device density, then manufacturing precision improves, but work function layers are damaged
Solution Approach 1:
The gate structure and dielectric layers are formed completely before any etching or patterning steps that could affect the work function layers. This preliminary formation of protective structures shields the work function layers from subsequent aggressive patterning processes, maintaining their integrity while achieving high precision
Solution Approach 2:
Multiple dielectric material layers are deposited beforehand to create a cushioning protective structure around the nanowires and gates. These layers absorb and distribute mechanical and chemical stresses from subsequent processing steps, preventing damage to the sensitive work function layers during aggressive patterning
Data Source
AI summary
A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.