GAA Nanostructure Gate Layout With Self-Aligned Wall Spacing
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Solution Overview
Problem
Current methods for integrating gate-all-around (GAA) devices in semiconductor manufacturing face challenges in achieving precise feature scaling and reducing complexity, particularly in forming gate structures around nanowires or nanosheets, which affect device performance and efficiency.
Innovation Solution
A semiconductor structure is formed using self-aligned processes to create wall structures between active regions and gate-cut features, allowing for reduced spacing and improved scaling, thereby enhancing device performance by reducing total cell capacitance and increasing on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography processes are used for pattern transfer, then manufacturing capability is maintained, but minimum feature size scaling is limited and manufacturing complexity increases
Solution Approach 1:
The patent introduces self-aligned spacer structures as intermediary elements that mediate between photolithography pattern transfer and the final sub-10nm feature formation. The spacers serve as a mediator that amplifies the pattern resolution beyond direct photolithography limits while maintaining manufacturing feasibility through self-aligned deposition and etching processes
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned structures by forming vertical spacers on patterned surfaces. This dimensional transition enables feature sizes smaller than what can be achieved through conventional planar photolithography, effectively moving the scaling problem into a different dimensional space
2Reliability
If gate structures are scaled down to improve device performance, then gate control is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The self-aligned spacer structures automatically position themselves relative to the gate and channel regions through conformal deposition and anisotropic etching processes. The spacer width is self-determined by the deposited material thickness rather than requiring precise photolithography alignment, making the system self-aligning and self-positioning without external intervention
Solution Approach 2:
The spacer structures are formed in advance as sacrificial elements that define the precise locations of subsequent gate and contact features. By preparing the spacer pattern beforehand through self-aligned processes, the positioning accuracy for later steps is predetermined and eliminated the need for high-precision alignment operations
3Reliability
If multi-gate structures are formed around nanowires/nanosheets, then gate control is improved, but integration difficulty increases
Solution Approach 1:
The complex multi-gate structure formation is divided into discrete, self-aligned steps: forming the nanowire/nanosheet channel, depositing spacer material on defined surfaces, selectively removing material to create gaps, depositing gate dielectric and conductive layers in subsequent self-aligned steps. Each segment builds upon the previous one with automatic alignment, breaking down the integration complexity into manageable modular operations
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first plurality of nanostructures between a first source/drain feature and a second source/drain feature, a first gate segment surrounding the first plurality of nanostructures, and a wall structure abutting the first gate segment. A first nanostructure in the first plurality of nanostructures includes a bulk portion and a protrusion, and the protrusion protrudes from a first sidewall of the bulk portion toward the wall structure.