GAA Gate Work Function Tuning for Multi-Threshold FETs
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to create FETs with different threshold voltages on the same substrate while managing the constraints of gate structure geometries and deposition challenges with continuous scaling down, particularly in gate-all-around (GAA) FETs and finFETs.
Innovation Solution
The solution involves forming PFETs with a similar work function metal layer but varying metal concentrations within high-K gate dielectric layers and bimetallic nitride layers to achieve different threshold voltages without altering the material or thickness of the work function metal layers, using metal doped regions and bimetallic nitride layers to adjust the effective work function values and threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different work function metal layers are used to achieve different threshold voltages, then threshold voltage differentiation is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies local quality by introducing metal doped regions at specific locations within the gate dielectric layer and at the gate electrode-dielectric interface. These localized metal dopants (such as aluminum, titanium, or tantalum) modify the work function locally without requiring different metal layers across the entire structure, thereby achieving threshold voltage differentiation while maintaining structural simplicity
Solution Approach 2:
The patent changes physical parameters by varying the concentration of metal dopants in the gate dielectric layer and at the interface. By adjusting the amount of metal doping (e.g., 10^19 to 10^21 atoms/cm³), the effective work function is tuned to achieve different threshold voltages for NFETs and PFETs on the same substrate, eliminating the need for complex multi-layer metal structures
2Manufacturing precision
If metal doped regions are added to adjust work function, then threshold voltage control is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by incorporating metal dopants into the gate dielectric layer during the dielectric deposition process itself, rather than adding them as a separate post-processing step. This allows the metal-doped dielectric to be formed in-situ using modified CVD or ALD processes, integrating the work function tuning into the existing manufacturing flow
Solution Approach 2:
The gate dielectric layer serves as an intermediary medium that contains the metal dopants. Instead of directly modifying the gate electrode or adding complex metal layers, the patent uses the dielectric layer as a carrier for metal dopants, which then indirectly adjust the work function through electric field effects and charge distribution modifications
3Quantity of substance
If continuous scaling down is pursued to increase storage capacity, then device density is improved, but manufacturing constraints and process complexity worsen
Solution Approach 1:
The patent changes material parameters by using high-k dielectric materials (such as hafnium oxide, zirconium oxide, or their silicates) with dielectric constants significantly higher than traditional SiO2. This allows for thinner effective oxide equivalents (EEQ) to achieve the same capacitance, enabling continued scaling while maintaining electrical performance and simplifying the manufacturing process compared to proportionally scaling all dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for cost-effective and time-efficient production of FETs with different threshold voltages, reducing manufacturing costs by 20-30% and time by 15-20%, and enabling smaller gate stack dimensions.
Implementation Method 1
forming a first metal doped region within a portion of the high-K gate dielectric layer
Implementation Method 2
a bimetallic nitride layer interposed between the high-K gate dielectric layer and the p-type work function metal layer
Data Source
AI summary
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.