GAA Transistor Inner Spacer Process for Uniform Gate Wraparound
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Solution Overview
Problem
Existing GAA transistor fabrication technologies face issues such as excessive impurity diffusion, increased built-in stress, undesired capacitance, and device degradation due to scaling down, leading to non-uniformity and performance variability.
Innovation Solution
A method involving the formation of a fin-shaped structure with alternating sacrificial and channel layers, followed by a replacement gate process, where sacrificial layers are selectively removed to form channel members, and a dielectric dummy layer is used to wrap around these members, with subsequent etching and deposition of inner spacer layers to create a uniform gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down to smaller technology nodes, then production efficiency increases and costs decrease, but excessive impurity diffusion, increased built-in stress, and device degradation occur
Solution Approach 1:
The channel region is divided into multiple channel members (e.g., nanowires or nanosheets) stacked vertically, allowing independent formation and control of each channel element. This segmentation enables better stress management and reduced impurity diffusion compared to a single large-channel device, as each channel member can be optimized independently while maintaining overall device performance at scaled dimensions.
Solution Approach 2:
The gate structure completely surrounds each channel member in a nested configuration, with the gate wrapping around the channel from top, bottom, and sidewalls. This gate-all-around structure provides maximum gate control over the channel while minimizing the footprint, enabling continued scaling without proportionally increasing gate-channel overlap and associated parasitic effects.
2Reliability
If gate structure extends around channel region to provide access on two or more sides, then gate control improves and off-state current reduces, but manufacturing complexity increases
Solution Approach 1:
A dummy gate structure is formed early in the fabrication process before the channel members are fully released and positioned. This preliminary gate structure serves as a template that guides subsequent processing steps, including the formation of spacers and the final gate-all-around structure. By establishing the gate footprint early, the method simplifies the overall manufacturing sequence despite the complex final structure.
Solution Approach 2:
Spacer structures are introduced as intermediary elements between the dummy gate and the final gate-all-around configuration. These spacers are formed on the sidewalls of the dummy gate and channel members, serving as temporary structures that define the gate extent and are later removed or transformed. This intermediary approach enables precise control of the gate structure formation while simplifying the manufacturing process.
3Ease of manufacture
If existing fabrication technologies are used for scaled devices, then manufacturing process remains simple, but etching loss and curvature profiles increase leading to non-uniformity
Solution Approach 1:
The fabrication method employs self-aligned processes where structures automatically define the positions of subsequent features. For example, the dummy gate and channel members serve as self-aligned references for spacer formation, and the spacers in turn define the final gate structure positions. This self-alignment eliminates the need for additional alignment steps and reduces variability, maintaining manufacturing simplicity while improving gate structure uniformity.
Data Source
AI summary
A method of the present disclosure includes forming over a substrate a stack that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, recessing a source/drain region of the fin-shaped structure to form a source/drain trench, selectively removing the sacrificial layers to release the channel layers as channel members, depositing a dielectric dummy layer between the channel members, laterally recessing the dielectric dummy layer to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming a source/drain feature in the source/drain region, removing the dummy gate stack, removing the dielectric dummy layer to release the channel members, and forming a gate structure to wrap around each of the channel members.