GAA Hard Mask Crystallization to Eliminate Seams and Voids
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing gate-all-around (GAA) devices with crystallized hard masks that have seams or voids, which affect the etch resistance and complexity of the manufacturing process.
Innovation Solution
A method involving the deposition of a metal-containing compound material and a stress material over semiconductor fins, followed by annealing to induce crystallization, which eliminates seams and voids in the hard mask by creating a high tensile or compressive stress field, resulting in a hard mask with improved etch resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional deposition method is used to form a hard mask, then the manufacturing process is simple, but the hard mask contains seams and voids that reduce etch resistance
Solution Approach 1:
The patent changes the physical and chemical parameters of the deposition process by introducing a stress material layer that generates tensile or compressive stress during annealing. This stress field modifies the crystallization behavior of the metal-containing compound material, transforming it from an amorphous state to a crystalline state that fills seams and voids, thereby improving etch resistance without significantly complicating the manufacturing process
Solution Approach 2:
The patent employs a composite structure consisting of a metal-containing compound material layer combined with a stress material layer. The stress material layer (containing materials like Si, Ge, or their oxides/nitrides) creates a stress field during annealing that induces crystallization in the metal-containing compound material. This composite approach enables the formation of a high-quality crystallized hard mask while maintaining process simplicity
2Manufacturing precision
If annealing is performed without stress induction, then the process is simple, but seams and voids remain in the hard mask
Solution Approach 1:
The patent applies preliminary action by depositing the stress material layer before the annealing process. This stress material layer is specifically designed to generate the necessary stress field during subsequent annealing, ensuring that the metal-containing compound material crystallizes properly and fills defects. The preliminary placement of the stress material simplifies the annealing process while achieving high manufacturing precision
Solution Approach 2:
The annealing process parameters are modified by the presence of the stress material layer, which introduces stress-induced parameter changes during heating. The stress field alters the crystallization kinetics and thermodynamics, enabling the formation of a defect-free crystalline structure at achievable temperatures and times, thereby improving hard mask quality without excessive process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a crystallized hard mask with reduced or no seams/voids, enhancing etch resistance and simplifying the manufacturing process for GAA devices by using stress-induced crystallization during the annealing process.
Implementation Method 1
annealing the metal-containing compound mask; annealing to induce crystallization
Implementation Method 2
creating a high tensile or compressive stress field, resulting in a hard mask with improved etch resistance
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent the semiconductor fin; forming a metal-containing compound mask over the isolation feature; annealing the metal-containing compound mask; forming a gate structure over a first portion of the semiconductor fin and a first portion of the metal-containing compound mask, wherein a second portion of the semiconductor fin and a second portion of the metal-containing compound mask are exposed by the gate structure; after forming the gate structure, etching back the second portion of the semiconductor fin; and forming a source/drain structure over the second portion of the semiconductor fin.