GAA HV-LV Transistor Co-Integration Using Channel Height Modulation
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Solution Overview
Problem
As transistor scaling continues, there is insufficient spacing between channel bodies in high voltage (HV) transistors to accommodate the thicker gate dielectric required by HV transistors, particularly in gate-all-around (GAA) configurations.
Innovation Solution
The channel bodies of HV transistors are selectively thinned or merged to create sufficient spacing for the thicker gate dielectric, while maintaining the same height for tip regions, allowing for co-integration with low voltage (LV) transistors in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor scaling is continued to increase integration density, then productivity and device density improve, but spacing between channel bodies becomes insufficient to accommodate thicker gate dielectric required by HV transistors
Solution Approach 1:
The patent applies local quality by creating different channel body heights in different regions: LV transistor channel bodies maintain full height while HV transistor channel bodies are selectively thinned. This allows the HV region to have sufficient vertical spacing for thicker gate dielectric while LV regions maintain high density with smaller spacing, resolving the contradiction between overall device density and local spacing requirements for HV operation
Solution Approach 2:
The patent segments the integrated circuit into distinct LV and HV transistor regions with different channel body configurations. By dividing the device structure into separate functional zones with different geometric parameters, each region can be optimized independently - LV regions for high density and HV regions for adequate dielectric spacing - thereby resolving the scaling contradiction
2Reliability
If thicker gate dielectric is used in HV transistors to accommodate high voltage operation, then voltage breakdown reliability improves, but device area and parasitic capacitance increase
Solution Approach 1:
The patent implements local quality by applying thicker gate dielectric exclusively to HV transistor regions where high voltage breakdown resistance is required, while LV transistor regions use thinner gate dielectric. This localized approach ensures adequate voltage breakdown protection for HV devices without unnecessarily increasing device complexity and parasitic capacitance across the entire integrated circuit
3Ease of manufacture
If channel bodies are thinned to create spacing for thicker gate dielectric, then ease of manufacture improves by enabling HV transistor formation, but channel body strength and current carrying capacity may deteriorate
Solution Approach 1:
The patent applies local quality by selectively thinning only the middle portions of channel bodies in HV transistor regions while preserving the tip regions that contact source and drain. This localized thinning provides the necessary spacing for gate dielectric formation and improves manufacturability of HV transistors while maintaining sufficient channel body strength and current carrying capacity through the preserved tip regions
Data Source
AI summary
An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.