Hybrid Standard Cell Structure for Dense Gate-All-Around IC Layout

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Solution Overview

Problem

The existing design of integrated circuits (ICs) using standard cells results in reduced packing density and performance due to pre-defined spacing rules between cells, leading to increased area requirements and yield degradation.

Innovation Solution

The implementation of a hybrid IC structure with large and small standard cells, each with distinct active region widths and channel configurations, placed edge-to-edge with shared gate stacks and dielectric gates to optimize packing density and performance, while maintaining consistent spacing for enhanced process window.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If pre-defined spacing rules are applied between standard cells, then manufacturing process window is improved, but packing density deteriorates

Engineering Contradiction:
Improveprocess windowVSAvoidcell area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent segments standard cells into different size categories (large and small cells) with distinct active region widths. Small cells have narrower active regions and can be placed closer together, while large cells have wider active regions. This segmentation allows the spacing rules to be applied selectively rather than uniformly, improving packing density while maintaining process window for each cell type.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different spacing requirements locally to different cell types rather than using a uniform spacing rule across all cells. Small cells with narrower active regions have different spacing requirements compared to large cells with wider active regions. This local quality approach allows optimized packing density in regions with small cells while maintaining adequate process window through appropriate spacing where required.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If uniform spacing is maintained between all standard cells, then process window is enhanced, but device performance deteriorates

Engineering Contradiction:
Improveprocess windowVSAvoiddevice performance
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent segments the standard cell library into different performance categories based on active region width. Small cells with narrower active regions are optimized for high-speed performance and can be placed in performance-critical paths, while large cells with wider active regions provide robustness for less critical functions. This segmentation allows the design to achieve high overall device performance while maintaining process window through appropriate cell selection and placement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the active region width parameter to create different cell types with distinct performance characteristics. Small cells have narrower active regions that enable faster switching speeds, while large cells have wider active regions that provide better manufacturing yield. By varying this parameter and allowing different cell types to coexist, the patent achieves both high device performance and adequate process window.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If standard cells are placed close together to increase packing density, then area efficiency is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improvecell areaVSAvoidprocess window
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent segments cells into small and large categories with different spacing requirements. Small cells with narrower active regions can be placed closer together without compromising manufacturing precision, achieving high packing density in regions where appropriate. Large cells maintain greater spacing to ensure adequate process window. This segmentation resolves the contradiction by allowing close placement only where it does not harm manufacturing precision.

Inventive Principle:
Principle #1Segmentation

4Area of stationary object

If hybrid cell structures with varying dimensions are used, then packing density is enhanced, but device complexity increases

Engineering Contradiction:
Improvecell areaVSAvoidcell configuration
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the standard cell library into a manageable two-category classification (small and large cells) based on active region width. This limited segmentation provides enough variety to achieve high packing density while avoiding the complexity of having many different cell types. The simple binary classification makes it easier to manage device complexity compared to having numerous dimensional variations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal standard cell library structure where both small and large cells follow the same basic design rules and can be placed using the same methodology. This universality allows the hybrid structure to achieve high packing density without proportionally increasing device complexity, as the same placement and routing tools can handle both cell types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12148745B2Integrated hybrid standard cell structure with gate-all-around device
Publication Date: 2024.11.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12148745B2 patent drawing
  • US12148745B2 patent drawing
  • US12148745B2 patent drawing

AI summary

The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.