Hybrid Standard Cell Structure with GAA Gates and Mixed Cell Pitches
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Solution Overview
Problem
The existing design of integrated circuits (ICs) using standard cells results in reduced packing density and performance due to pre-defined spacing rules between cells, leading to increased area requirements and yield degradation.
Innovation Solution
The implementation of a hybrid IC structure with large and small standard cells of varying active region widths and pitches, where the large cells have wider nanosheet channels and the small cells have narrower nanosheet channels, all with continuous gate stacks and dielectric gates for enhanced packing density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-defined spacing rules are applied between standard cells, then design rules are followed and cells are placed in desired locations, but the reserved space between cells results in significant increase in cell areas and reduced packing density
Solution Approach 1:
The patent applies different spacing rules to different regions of the standard cell layout. Specifically, smaller spacing is used between cells of the same type (e.g., nFET-nFET or pFET-pFET pairs), while larger spacing is used between cells of different types. This local differentiation allows optimization of packing density in critical regions while maintaining necessary isolation where required, thereby reducing overall cell area without sacrificing placement precision.
Solution Approach 2:
The standard cell layout is segmented into different regions with different spacing characteristics. The cell is divided into zones where tight spacing is applied to adjacent transistors of the same type, and relaxed spacing is applied to transistors of different types or at cell boundaries. This segmentation enables the design to achieve high packing density in active regions while maintaining design rule compliance and electrical isolation where needed.
2Manufacturing precision
If pre-defined spacing rules are applied between standard cells, then design rules are followed, but the reserved space results in significant increase in cell areas and degraded performance
Solution Approach 1:
The patent implements location-specific spacing optimization where minimal spacing is used between transistors that require strong electrical coupling or matching (such as differential pairs), while larger spacing is used where electrical isolation is paramount. This local quality approach ensures that device performance is optimized in critical regions without uniformly increasing spacing across the entire cell, thereby maintaining high reliability while minimizing area impact.
Solution Approach 2:
The spacing between standard cells is made dynamic rather than static, allowing the design to adapt spacing based on the specific functional requirements of different cell regions. Critical pairs of transistors receive optimized minimal spacing for performance, while non-critical regions use standard spacing for isolation. This dynamic approach to spacing allocation maintains device performance while reducing overall cell area compared to uniform spacing rules.
3Device complexity
If uniform spacing is used between all standard cells, then design simplicity is maintained, but packing density and performance are degraded
Solution Approach 1:
The patent replaces uniform spacing with local quality-based spacing, where different spacing values are applied to different regions based on their specific requirements. Adjacent transistors of the same type use minimal spacing to maximize packing density, while transistors of different types or at cell boundaries use larger spacing for isolation. This approach increases packing density significantly while adding manageable complexity through systematic regional differentiation rather than complete layout complexity.
Solution Approach 2:
The patent optimizes spacing in multiple dimensions rather than applying a single uniform spacing rule. By considering spacing in both horizontal and vertical directions differently, and by applying spacing rules at different hierarchical levels (within cells, between cells, between cell types), the design achieves higher packing density. This multi-dimensional spacing optimization provides a structured approach that balances density improvement with design manageability.
Data Source
AI summary
The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.