Stacked Gate-All-Around IC Layout for Lower Cell Height
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Solution Overview
Problem
As integrated circuits shrink, there is a need to reduce their area and improve power grid distribution while maintaining routing flexibility, which is challenging due to the constraints of transistor layout and power line configurations.
Innovation Solution
The configuration involves stacking transistors with gate-all-around structures and power lines disposed on opposite sides, where the power line VSS has a larger area than VDD, allowing for improved routing flexibility and increased density by forming power lines with critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are stacked with gate-all-around structures and power lines are disposed on opposite sides, then cell height is reduced and density is increased, but routing flexibility is constrained
Solution Approach 1:
The patent transitions from planar power line arrangement to three-dimensional stacking with gate-all-around structures. Power lines VDD and VSS are disposed on opposite sides of the stacked transistor structure, utilizing vertical dimension to reduce cell height while maintaining routing flexibility through the asymmetric area configuration of power lines.
Solution Approach 2:
The patent employs asymmetric configuration where the power line VSS has a larger area than the power line VDD. This asymmetric design allows optimization of power distribution while accommodating routing requirements, balancing the contradiction between compact cell height and routing flexibility.
2Reliability
If power line VSS has larger area than VDD, then power grid distribution is enhanced, but area occupied increases
Solution Approach 1:
The patent applies local quality by giving different areas to power lines VDD and VSS based on their specific functional requirements. The power line VSS is designed with larger area to enhance power grid distribution and reduce resistance, while the power line VDD maintains smaller area, optimizing overall power delivery without uniformly increasing the occupied area.
3Area of stationary object
If transistors are shrunk to decrease layout area, then integrated circuit area is reduced, but power grid distribution and routing flexibility become more challenging
Solution Approach 1:
The patent addresses transistor shrinking challenges by moving to three-dimensional stacked structures with gate-all-around configurations. This vertical stacking reduces lateral layout area while the multi-layer power line arrangement on opposite sides provides robust power grid distribution, effectively decoupling area reduction from power distribution complexity.
Solution Approach 2:
The patent combines multiple functions into the stacked transistor structure with gate-all-around configuration, integrating power distribution, signal routing, and transistor functionality in a compact vertical arrangement. This merging reduces overall layout area while maintaining power grid effectiveness through the coordinated design of power lines VDD and VSS on opposite sides.
Data Source
AI summary
An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.