GAA Inner Spacer Formation for Precise Nanowire Channel Control
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Solution Overview
Problem
Current methods for forming inner spacers in gate-all-around (GAA) transistors face challenges in accurately controlling dimensions and positions, leading to variability in channel length and potential damage to nanowire channels during the etching process, which affects device performance.
Innovation Solution
A cyclic process is employed that alternates between surface treatment and selective etching to precisely remove the inner spacer material layer, ensuring accurate control of inner spacer dimensions and maintaining the integrity of nanowire channels, thereby improving channel length uniformity and reducing excess etching-related damages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used to form inner spacers, then inner spacer formation is achieved, but dimension control precision deteriorates and nanowire channel damage occurs
Solution Approach 1:
The patent segments the inner spacer formation process into multiple discrete steps: depositing sacrificial layers, selective removal of sacrificial layers, depositing inner spacer material, and selective etching. This segmentation allows precise control at each stage and prevents excessive etching that would damage nanowire channels.
Solution Approach 2:
The patent applies preliminary actions by first depositing sacrificial layers (e.g., SiGe) before forming the inner spacers. These sacrificial layers are selectively removed to create space for inner spacers, and the process includes preliminary surface treatments (oxidation/nitridation) to protect nanowires before etching occurs.
Solution Approach 3:
The patent changes material parameters by using different materials with distinct etch selectivities (SiGe sacrificial layers, silicon nitride inner spacers, silicon oxide barriers). It also changes etching parameters through cyclic processes alternating between surface treatment and selective etching, controlling etch depth and duration to prevent nanowire damage.
2Reliability
If inner spacer formation is performed to reduce capacitance and prevent leakage, then device performance is improved, but channel length uniformity deteriorates due to dimension control issues
Solution Approach 1:
The patent implements feedback control through cyclic processes where surface treatment and selective etching alternate. Each cycle provides feedback on the etching progress, allowing precise termination before nanowire damage occurs. The process monitors and adjusts etching duration and intensity to maintain consistent inner spacer dimensions and channel length uniformity.
Solution Approach 2:
The patent employs periodic action through cyclic etching processes that alternate between surface treatment steps and selective etching steps. This periodic approach allows controlled removal of material in manageable increments, ensuring uniform channel length across multiple nanowires while preventing excessive etching.
3Ease of manufacture
If excess etching is performed during inner spacer formation, then inner spacer formation is completed, but nanowire channel integrity deteriorates
Solution Approach 1:
The patent uses intermediary materials and processes: sacrificial layers (SiGe) that are selectively removed, barrier layers (silicon oxide, silicon nitride) that protect nanowires, and surface treatments (oxidation, nitridation) that create protective surfaces. These intermediaries enable complete inner spacer formation while preventing direct contact between etchants and nanowire channels.
Solution Approach 2:
The patent converts the potentially harmful etching process into a beneficial selective removal process. By using cyclic etching with surface treatments, the harmful excess etching is transformed into a controlled process that removes sacrificial materials and forms inner spacers while simultaneously protecting nanowires through alternating treatment and etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of inner spacer formation, maintains the integrity of nanowire channels, and avoids high parasitic capacitances, leading to improved device performance and reliability.
Implementation Method 1
selectively etching the surface portion of the dielectric material layer
Implementation Method 2
performing a treatment process to a surface portion of the dielectric material layer
Implementation Method 3
forming a gate structure engaging the nanowires
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.