GAA Inner Spacer De-Seaming for Thickness and Short Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of inner spacers in gate-all-around transistors during the replacement gate process results in seams and dishing, leading to etching loss and thinner than expected spacer thickness, which affects parasitic capacitance and can cause shorts between the gate structure and epitaxial source/drain features.
Innovation Solution
A de-seaming process is implemented during inner spacer formation, involving conformal deposition and controlled etching to eliminate seams and ensure adequate spacer thickness, using multiple layers of dielectric materials with varying etching resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are formed during the replacement gate process, then gate control is improved, but seams and dishing occur leading to etching loss and reduced spacer thickness
Solution Approach 1:
The inner spacer formation process is divided into multiple sequential deposition steps (first dielectric layer, second dielectric layer, third dielectric layer) with intermediate etching steps. This segmentation allows each layer to be optimized independently, preventing seams and dishing that would occur with single-step deposition, thereby maintaining precise spacer thickness while achieving reliable gate control.
Solution Approach 2:
The first dielectric layer is deposited and etched back before forming the second dielectric layer. This preliminary action creates a prepared surface that prevents seam formation in subsequent layers, ensuring uniform spacer thickness from the outset rather than attempting to correct defects after complete spacer formation.
2Device complexity
If conventional inner spacer deposition is used, then process simplicity is maintained, but parasitic capacitance increases due to thinner spacers
Solution Approach 1:
The inner spacer is constructed as a composite structure with three different dielectric layers, each with potentially different material properties and etching characteristics. This composite approach enables precise control of the final spacer thickness and electrical properties, reducing parasitic capacitance while the systematic process design keeps complexity manageable through modular deposition and etching steps.
3Productivity
If single-layer dielectric deposition is used, then manufacturing steps are reduced, but shorts occur between gate structure and source/drain features
Solution Approach 1:
Each dielectric layer is deposited with specific local properties optimized for its function: the first layer provides a foundation with controlled etch resistance, the second layer addresses seam prevention, and the third layer ensures adequate final thickness. This local optimization of each layer's quality ensures sufficient spacer thickness throughout to prevent shorts, while the systematic approach maintains manufacturing efficiency.
Solution Approach 2:
The multi-layer structure with intermediate etching steps acts as a cushioning mechanism that prevents potential shorts before they occur. By building up the spacer thickness in controlled increments and removing excess material at intermediate stages, the process ensures adequate insulation is achieved without relying on a single high-risk deposition step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the reliability of inner spacers by preventing excessive etching loss and maintaining optimal thickness, reducing parasitic capacitance and minimizing the risk of shorts, thereby improving the performance and integrity of gate-all-around transistors.
Implementation Method 1
depositing a first dielectric layer in the inner spacer recesses
Implementation Method 2
etching back the first dielectric layer opens the seam
Implementation Method 3
depositing a second dielectric layer seals the seam inside the inner spacer
Implementation Method 4
etching back the second dielectric layer to form inner spacers
Data Source
AI summary
A method includes forming over a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, recessing a source/drain region of the fin-shaped structure, selectively removing the sacrificial layers in the channel region to release the channel layers as channel members, depositing a dummy layer in space between the channel members, selectively and partially recessing the dummy layer to form inner spacer recesses, depositing a first dielectric layer in the inner spacer recesses, etching back the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, etching back the second dielectric layer to form inner spacers in the inner spacer recesses, forming a source/drain feature over the source/drain region, removing the dummy gate stack and the dummy layer, and forming a gate structure to wrap around the channel members.