GAA Inner Spacer Structure for Selective Etching Control
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Solution Overview
Problem
In the fabrication of gate-all-around (GAA) transistors, the etching selectivity between inner spacer features and sacrificial materials is often inadequate, leading to inconsistent gate structure profiles and potential damage to epitaxial source/drain features during the removal of sacrificial layers.
Innovation Solution
A method involving the sequential deposition and selective etching of first and second inner spacer layers, where the first layer is chosen to be resistant to the etchant used for the dummy layer, ensuring precise formation of inner spacer features and protecting the source/drain regions, followed by the replacement of a dummy gate stack with a functional gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single inner spacer layer is used, then the fabrication process is simpler, but the etching selectivity between inner spacer features and sacrificial materials is inadequate, leading to inconsistent gate structure profiles
Solution Approach 1:
The single inner spacer layer is divided into two distinct layers: a first inner spacer layer with high etching selectivity relative to sacrificial materials, and a second inner spacer layer with different etching characteristics. This segmentation allows each layer to perform its function optimally, with the first layer providing precise profile definition and the second layer offering structural support, thereby resolving the contradiction between process simplicity and manufacturing precision.
Solution Approach 2:
The patent employs composite material structure by combining two different inner spacer layers with distinct material properties. The first inner spacer layer is made of a material exhibiting high etching selectivity against sacrificial materials, while the second layer uses a different material composition. This composite approach enables simultaneous achievement of precise gate profile formation and structural integrity, overcoming the limitations of using a single material layer.
2Productivity
If sacrificial layers are removed without protective measures, then the fabrication process is faster, but epitaxial source/drain features may be damaged
Solution Approach 1:
The first inner spacer layer is formed beforehand to serve as a protective barrier before the sacrificial layers are removed. This preliminary protective structure is specifically designed with high etching selectivity, allowing the sacrificial materials to be selectively removed while the inner spacer features remain intact, thereby protecting the underlying epitaxial source/drain features from damage during the removal process.
Solution Approach 2:
The first inner spacer layer acts as an intermediary protective layer between the etching process and the epitaxial source/drain features. It mediates the interaction by providing a selectively resistant barrier that allows controlled removal of sacrificial materials while preventing direct contact between the etchant and the delicate epitaxial structures, thus maintaining feature integrity without significantly extending the fabrication timeline.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent gate structure profiles and protects epitaxial source/drain features, enhancing the reliability and performance of GAA transistors by maintaining precise etching control and minimizing damage.
Implementation Method 1
The composition of the first inner spacer layer is selected such that it is not substantially etched when the dummy layer is etched away
Implementation Method 2
multi-gate metal-oxide-semiconductor field effect transistor (multi-gate MOSFET, or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling
Data Source
AI summary
A method of the present disclosure includes forming a stack including channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming an isolation feature, forming a dummy gate stack over a channel region of the fin-shaped structure, depositing a gate spacer layer over the dummy gate stack, recessing a source/drain region of the fin-shaped structure, selectively removing the sacrificial layers to release the channel layers channel members, depositing a dummy layer over the channel members, selectively and partially recessing the dummy layer to form inner spacer recesses, depositing a first inner spacer layer and a second inner spacer layer over the inner spacer recesses, etching back the first inner spacer layer and the second inner spacer layer to form inner spacer features, forming a source/drain feature, removing the dummy layer, and forming a gate structure to wrap around each of the plurality of channel members.