GAA FET Inner Spacer Formation Using Modulated Sacrificial Layers
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Solution Overview
Problem
In the manufacturing of semiconductor devices, particularly fin field effect transistors (FinFETs) and gate-all-around (GAA) FETs, controlling lateral etching during the release of nanowires and forming uniform inner spacers between the metal gate electrode and source/drain epitaxial layers is challenging, leading to issues with gate control capability and increased gate-to-drain capacitance, which affects circuit speed and process uniformity.
Innovation Solution
The use of modulated composition sacrificial semiconductor layers, specifically varying the germanium concentration, allows for controlled lateral etching and the formation of curved-shaped inner spacers, improving gate control and reducing channel resistance by employing wet etching techniques to achieve precise spacer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to release nanowires, then the etching process is simple, but lateral etching cannot be controlled and inner spacers are non-uniform
Solution Approach 1:
The patent applies local quality by creating composition gradients within the sacrificial semiconductor layers. The germanium concentration varies spatially (higher at edges, lower at center), causing different etching rates in different regions. This enables controlled lateral etching at the edges while protecting the center, resulting in uniform curved inner spacers with rounded ends.
Solution Approach 2:
The patent changes the compositional parameters of the sacrificial semiconductor layers by modulating germanium concentration. This parameter change enables selective etching behavior where regions with different Ge concentrations etch at different rates, allowing precise control over lateral etching extent and inner spacer formation.
2Reliability
If lateral etching is not controlled, then the process is straightforward, but gate control capability deteriorates and gate-to-drain capacitance increases
Solution Approach 1:
By implementing local quality through composition gradients, the patent achieves controlled lateral etching that maintains proper spacing between the gate electrode and source/drain regions. This prevents excessive gate-to-drain overlap, reducing parasitic capacitance and improving gate control without significantly complicating the manufacturing process.
3Manufacturing precision
If uniform inner spacers are formed on 12-inch wafers, then process uniformity improves, but achieving consistent composition control across the large substrate becomes more difficult
Solution Approach 1:
The patent uses parameter changes by implementing composition gradients that can be controlled through deposition parameters. By adjusting deposition conditions (such as radial source distribution or deposition rate profiles), consistent composition gradients can be achieved across large 12-inch wafers, enabling uniform inner spacer formation despite the large substrate area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more precise control over the thickness, shape, and location of inner spacers, thereby enhancing gate control capability and reducing capacitance, leading to improved process uniformity and circuit performance, especially on larger wafers like 12-inch substrates.
Implementation Method 1
employing wet etching techniques to achieve precise spacer formation
Implementation Method 2
allows for controlled lateral etching and the formation of curved-shaped inner spacers
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.