Amorphous Silicon Inner Spacer Liner for GAA Silicon Loss Control
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Solution Overview
Problem
The challenge in CMOS wafer manufacturing and GAA device formation is the significant silicon loss during the selective-etch process, which leads to parasitic capacitance and degraded DC performance, particularly in thinner channel layers.
Innovation Solution
A method involving the formation of a superlattice structure on a semiconductor substrate, followed by the deposition of an amorphous silicon liner and an inner spacer, which is conformally formed along the recessed semiconductor material layers and channel layers, to reduce silicon loss and improve electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a selective-etch process is used to create the indent/cavity for inner spacer formation, then the inner spacer can be formed to provide electrostatic control, but significant silicon loss occurs at the indent/cavity corner which reduces current pathway and degrades DC performance
Solution Approach 1:
The patent applies preliminary action by forming the amorphous silicon liner conformally on the semiconductor material layers before the selective etch process creates the indent/cavity. This pre-formed liner is positioned to extend into the cavity region, so when silicon is removed during etching, the liner remains to compensate for the upcoming silicon loss and maintain the current pathway.
Solution Approach 2:
The amorphous silicon liner acts as a compensatory structure that cushions against the harmful effect of silicon loss. By having this liner in place beforehand, the patent compensates for the inevitable silicon removal during the selective etch process, ensuring that the current pathway is maintained and DC performance is preserved while still achieving the required electrostatic control.
2Ease of manufacture
If the selective-etch process is used to form the indent/cavity, then inner spacer formation is enabled, but parasitic capacitance increases due to unavoidable silicon loss
Solution Approach 1:
The amorphous silicon liner is formed in advance before the selective etch process, positioned to compensate for the silicon that will be removed. This preliminary formation enables the indent/cavity to be created for inner spacer formation while the liner prevents the generation of excessive parasitic capacitance by maintaining proper silicon geometry.
3Area of stationary object
If thinner channel layers are used to reduce device size, then circuit density increases, but DC performance is significantly degraded due to silicon loss
Solution Approach 1:
The amorphous silicon liner is formed preliminarily on the thinner channel layers before the selective etch process. This liner compensates for the silicon loss that would otherwise significantly impact the already-thin current pathway, thereby enabling the use of thinner channel layers for reduced device size while preserving DC performance.
Solution Approach 2:
The patent applies local quality by providing the amorphous silicon liner specifically at critical locations where silicon loss would have the greatest impact on DC performance, such as the indent/cavity corner regions. This localized compensation allows thinner channel layers to maintain adequate current pathways without requiring uniform thickening across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces silicon loss, enhances DC performance, and lowers effective capacitance, resulting in improved GAA device performance and yield, especially in SRAM applications.
Implementation Method 1
forming an amorphous silicon liner conformally along the electronic device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers
Data Source
AI summary
Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.