Inner Spacer Trimming in GAA Fin Structures for Reliable Scaling
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting the reliability and performance of semiconductor devices.
Innovation Solution
The process involves forming fin structures and gate-all-around (GAA) transistor structures using double-patterning or multi-patterning techniques, with sacrificial layers and spacers, followed by epitaxial growth and selective etching to create channel structures and source/drain regions, and trimming gate and inner spacers to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows complex device formation to be broken down into manageable steps that can be executed with existing fabrication capabilities.
Solution Approach 2:
Different regions of the semiconductor device are formed with distinct properties through selective epitaxial growth where semiconductor layers are grown only in specific trench regions, and selective doping where dopant layers are deposited only in certain areas. This local differentiation enables complex device functionality without requiring uniformly complex fabrication processes across the entire chip.
2Length of stationary object
If feature sizes continue to decrease, then geometric scaling benefits are achieved, but manufacturing reliability deteriorates
Solution Approach 1:
Sacrificial layers are formed in advance in specific regions before the main device fabrication steps. These pre-formed structures serve as templates and protection layers that guide subsequent processing steps, ensuring that critical dimensions are maintained even as overall feature sizes decrease. The sacrificial layers are removed only when they have served their guiding purpose.
Solution Approach 2:
Sacrificial layers act as intermediary structures that mediate between the photolithography pattern and the final device structure. These intermediate layers enable the formation of complex multi-depth trench structures and selective region definitions without requiring direct patterning at each stage, thereby maintaining manufacturing reliability through indirect, controlled formation processes.
3Manufacturing precision
If double-patterning or multi-patterning techniques are used to form fin structures and GAA transistor structures, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent extends patterning precision into the vertical dimension by forming trenches at different depths (first trench extending to first depth, second trench extending to second depth greater than first depth). This vertical dimensionality allows multi-patterning effects to be achieved through depth-based differentiation rather than only through lateral multi-step patterning, reducing overall process complexity.
Solution Approach 2:
The fabrication process nests multiple structures within each other: sacrificial layers are formed within trenches, then semiconductor layers are epitaxially grown within the trench regions, followed by doping layers deposited within specific regions. This nested structure formation allows complex multi-layer devices to be created through sequential, contained processing steps rather than requiring simultaneous complex patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices with improved performance and reliability by allowing for smaller feature sizes and precise control over transistor structures, enhancing current flow and reducing parasitic capacitance.
Implementation Method 1
forming an epitaxial structure on the side surfaces of the semiconductor layers
Data Source
AI summary
A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.