Wrap-Around Inner Spacer Structure for Uniform GAA Gate Length
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Solution Overview
Problem
Existing gate-all-around field effect transistors face issues with rounding and narrowing of inner spacers adjacent to outer spacers due to etching effects, leading to weak points at the interface and inconsistent device performance.
Innovation Solution
Incorporation of an inner spacer liner that is selectively recessed to expose sacrificial layers, forming a uniform indent process and a wrap-around-channel inner spacer, ensuring consistent gate length and improved isolation between conductive components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer formation is used, then the device structure is simple, but rounding and narrowing occur at the inner spacer interface leading to weak points and inconsistent device performance
Solution Approach 1:
The inner spacer structure is segmented into multiple functional components: a first inner spacer portion formed at a first height, a second inner spacer portion formed at a second height, and a third inner spacer portion formed at a third height. This segmentation allows each portion to serve specific functions in preventing rounding and narrowing, thereby improving device performance consistency without creating a monolithic complex structure.
Solution Approach 2:
The inner spacer portions are nested within the gate structure, with each subsequent portion positioned at different heights and wrapping around the channel. The first inner spacer portion is nested within the gate, the second portion extends outward, and the third portion provides additional wrapping protection. This nesting approach maintains structural integrity while preventing interface weak points.
2Manufacturing precision
If inner spacer formation without selective recessing is used, then the manufacturing process is simple, but etching effects cause rounding and narrowing at the inner spacer interface
Solution Approach 1:
A liner is formed on the inner spacer structure before the etching process. This preliminary protective layer prevents etching-induced rounding and narrowing at the inner spacer interface. The liner is subsequently removed in a controlled manner, leaving the inner spacer with uniform dimensions and no weak points, thereby achieving high manufacturing precision.
Solution Approach 2:
The liner acts as an intermediary protective layer between the etching process and the inner spacer structure. It mediates the harmful effects of etching by providing a sacrificial barrier that protects the inner spacer from rounding and narrowing, ensuring dimensional uniformity throughout the manufacturing process.
3Manufacturing precision
If wrap-around-channel inner spacer is implemented, then gate length uniformity and isolation are improved, but the fabrication process becomes more complex
Solution Approach 1:
The inner spacer structure exhibits local quality variations with different portions having distinct functions and geometries. The first portion provides base support, the second portion extends outward for wrapping, and the third portion provides additional lateral coverage. This localized differentiation ensures uniform gate length control while managing fabrication complexity through functional specialization.
Solution Approach 2:
The inner spacer structure transitions from a single-plane configuration to a multi-dimensional wrap-around structure. The first portion is formed at a first height, the second portion at a second height, and the third portion at a third height, creating a three-dimensional configuration that provides comprehensive gate length control and lateral isolation, thereby achieving superior manufacturing precision.
Data Source
AI summary
A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.


