Gate-All-Around Transistor Inner Spacers for Nanosheet Insulation
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Solution Overview
Problem
Effective insulation of semiconductor nanosheets in gate all around transistors is challenging, which affects the performance and reliability of these transistors.
Innovation Solution
The use of sacrificial semiconductor regions with different compositions for selective etching, allowing for the formation of high-quality dielectric spacers that improve insulation and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single spacer structure is used, then manufacturing process is simpler, but insulation effectiveness is insufficient
Solution Approach 1:
The single spacer structure is divided into two distinct spacers: a first spacer formed on the semiconductor nanosheet and a second spacer formed on the first spacer. This segmentation allows each spacer to perform specific insulation functions, improving overall insulation effectiveness while maintaining manageable structural complexity through modular design.
Solution Approach 2:
The insulation structure is extended from a single layer to multiple layers in the vertical dimension. The first spacer provides initial insulation, and the second spacer adds an additional insulation layer, creating a multi-layered insulation system that enhances effectiveness without significantly increasing lateral complexity.
2Manufacturing precision
If sacrificial semiconductor regions with different compositions are used, then insulation quality is improved, but manufacturing process complexity increases
Solution Approach 1:
Sacrificial semiconductor regions with different compositions are placed at specific locations: one sacrificial region is formed on the semiconductor nanosheet and another is formed on the first spacer. Each sacrificial region has a composition optimized for its specific location, allowing selective etching to create high-quality dielectric spacers with precise local properties.
Solution Approach 2:
The composition of sacrificial semiconductor regions is varied to achieve different etching rates and characteristics. By changing the material composition parameter of the sacrificial regions, the etching process can be optimized to produce dielectric spacers with desired properties while managing process complexity through controlled parameter variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the AC performance of transistors, maintains the integrity of semiconductor nanosheets, and eliminates the need for complex recess loading processes, resulting in improved transistor performance and processing yields.
Implementation Method 1
sacrificial semiconductor regions with different compositions for selective etching
Data Source
AI summary
A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.