Gate-All-Around Semiconductor Structure With Inner Spacers
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Solution Overview
Problem
The challenge of short-channel effects in MOSFETs, particularly in gate-all-around transistors, arises from the difficulty in controlling the channel due to reduced gate structure effectiveness as device sizes shrink, leading to subthreshold leakage and poor performance.
Innovation Solution
A semiconductor structure design with inner spacers embedded in the source-drain doped layer, allowing the gate structure to surround the channel from all sides, and a fabrication method where the source-drain doped layer is grown first, followed by forming inner spacers, to enhance channel control and improve growth quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is reduced to adapt to smaller feature sizes, then the device can scale down, but the gate structure's ability to control the channel deteriorates, leading to short-channel effects and subthreshold leakage
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional gate-all-around control, where the gate structure wraps around the channel from all sides (top, bottom, and sidewalls). This dimensional change provides superior electrostatic control over the channel, effectively suppressing short-channel effects even at reduced channel lengths while maintaining scalability.
Solution Approach 2:
The gate structure is nested around the channel in a concentric arrangement, with the gate completely surrounding the channel region. This nested configuration maximizes the gate's control authority over the channel, ensuring effective pinch-off and suppression of leakage currents despite the reduced channel dimensions.
2Ease of manufacture
If inner spacers are formed before growing the source-drain doped layer, then the structure can be fabricated, but grain boundaries form in the source-drain doped layer, affecting stress and performance
Solution Approach 1:
The source-drain doped layer is grown in advance before the inner spacers are formed. This preliminary action allows the source-drain layer to be grown as a continuous, high-quality film without interruption. Subsequently, the inner spacers are formed by etching recesses into the already-grown source-drain layer, avoiding any grain boundary formation that would occur if growth were attempted on pre-formed spacer structures.
Data Source
AI summary
A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The method includes providing a base substrate, where a stacked layer structure, including sacrificial layers and channel layers, and a dummy gate structure are formed on the base substrate; forming a source-drain doped layer on the base substrate; removing the dummy gate structure to form a gate opening; removing the sacrificial layers to form through-grooves and a channel layer structure including the channel layers spaced apart from each other; forming inner spacers in the source-drain doped layer; and forming a gate structure crossing the channel layer structure in the gate opening and the through-grooves. The gate structure surrounds the channel layers; and the gate structure between adjacent channel layers and between the channel layer structure and the base substrate is spaced apart from the source-drain doped layer by the inner spacers.