GAA Dielectric Interposer Cleaning for Channel Length Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for gate-all-around (GAA) transistors face challenges such as epitaxial loss in the source/drain region, variation of channel lengths, and weak regions of gate electrodes, especially as device size is scaled down, leading to degraded performance and increased complexity in IC processing.
Innovation Solution
A method involving the use of a dummy interposer or dummy oxide interposer, along with specific cleaning processes to eliminate etch residues and defects, and enhancing channel dimensions and profile, including selective etching and controlled cleaning solutions to maintain gate control and reduce SCEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is scaled down to increase functional density, then production efficiency and cost are improved, but manufacturing precision and reliability deteriorate due to epitaxial loss, channel length variation, and weak gate electrodes
Solution Approach 1:
The method performs preliminary actions by forming dummy gate structures and performing selective etching before final device fabrication. The dummy gates are formed to define channel regions, and selective etching is performed to remove sacrificial materials while preserving the desired channel length, thereby preventing channel length variation before it occurs
Solution Approach 2:
The patent introduces dummy gate structures as intermediary elements that facilitate precise channel length definition. These dummy gates act as mediators between the patterning process and the final device structure, enabling accurate channel length control through selective removal processes
2Productivity
If device size is scaled down to increase functional density, then production efficiency and cost are improved, but device reliability deteriorates due to epitaxial loss and weak gate electrodes
Solution Approach 1:
The method changes processing parameters by using selective etching conditions that differ for dummy gates versus actual device structures. By controlling etch selectivity and performing cleaning processes at specific stages, the patent maintains device reliability while enabling scaled production
Solution Approach 2:
The patent converts the potential harm of epitaxial loss into a benefit by using selective etching to remove sacrificial dummy gate materials. The controlled removal process actually improves device quality by eliminating defects and ensuring precise channel formation, turning a scaling challenge into a quality enhancement opportunity
3Reliability
If conventional GAA device methods are used to achieve gate-all-around structure, then gate control is improved, but manufacturing complexity increases due to multiple etching and cleaning processes
Solution Approach 1:
The patent segments the fabrication process into distinct stages with specific cleaning operations at each stage. By dividing the complex manufacturing process into manageable segments (forming dummy gates, selective etching, intermediate cleaning, final device formation), the patent maintains gate control while making the overall process more controllable and less complex
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the performance of GAA devices by reducing defects and maintaining channel dimensions, thereby enhancing gate control and mitigating short-channel effects, while maintaining device integrity during scaling.
Implementation Method 1
performing a cleaning process using a cleaning chemical solution to the first semiconductor layers and the dummy interposer
Data Source
AI summary
The present disclosure provides a method that includes forming a stack including first semiconductor layers and second semiconductor layers over a substrate, the first and second semiconductor layers alternating with one another; forming a dummy gate structure over the stack; selectively removing the second semiconductor layers of the stack, resulting in first gaps among the first semiconductor layers; depositing a first dielectric material to fill in the first gaps; performing a first etching process to the first dielectric material to form dielectric interposers; performing a first cleaning process using a first cleaning chemical solution; performing a second etching process to laterally recess the dielectric interposers, resulting in second gaps among the first semiconductor layers; and performing a second cleaning process using a second cleaning chemical solution being different from the first cleaning chemical solution.