Gate-All-Around I/O Dielectric Stack for Breakdown Reliability
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Solution Overview
Problem
The formation of horizontal source/drain extensions in narrow and tall finFETs is challenging due to damage from conventional ion implantation, leading to intermixing between silicon channel and silicon-germanium layers, and thermal anneal increases the thermal budget, while space confinement in horizontal gate-all-around devices limits the thickness of gate dielectric material.
Innovation Solution
A method involving the formation of alternating silicon and silicon-germanium layers, patterning, and etching to expose sidewalls, followed by an enhanced in situ steam generation process to form a thermal oxide layer, passivation, and deposition of a low-κ layer using atomic layer deposition, which densifies and passivates the low-κ layer to enhance the gate-all-around transistor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ion implantation is used to form horizontal source/drain extensions in finFETs, then doping can be achieved, but the fin-shaped channel region becomes amorphized or damaged and intermixing occurs between silicon channel and silicon-germanium layers
Solution Approach 1:
The patent replaces conventional ion implantation (mechanical/physical process) with a selective epitaxial growth process (chemical process) to form source/drain extensions. This substitution eliminates the damage and intermixing caused by ion bombardment while achieving precise doping through controlled silicon-germanium layer formation and selective removal.
Solution Approach 2:
The patent changes the fundamental parameter of the doping process from physical ion implantation to chemical epitaxial growth. By controlling temperature, pressure, and gas flow during selective epitaxial growth, precise doping is achieved without the mechanical damage inherent in ion implantation, thereby improving channel region integrity.
2Reliability
If thermal anneal is performed to repair implant damage in finFETs, then channel region damage can be repaired, but the thermal budget of the device increases
Solution Approach 1:
The patent replaces the thermal annealing process (thermal treatment) with selective epitaxial growth (chemical process) to repair and form source/drain extensions. This approach repairs channel region damage without requiring high-temperature thermal annealing, thereby reducing the thermal budget while maintaining reliability.
3Reliability
If gate dielectric material thickness is increased to improve I/O transistor performance, then electrical performance improves, but space confinement between pillars in hGAA devices prevents sufficient thickness
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers with different materials and properties. This composite approach allows achieving the required electrical performance (equivalent oxide thickness) within the limited physical space by combining thin high-k dielectric layers with low-k spacer layers, optimizing both electrical performance and spatial constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the effective electrical thickness and reduces bulk traps, enhancing the breakdown performance and reliability of gate-all-around transistors by maintaining the thin thermal oxide interface and low-κ dielectric layer combination.
Implementation Method 1
forming a thermal oxide layer on the silicon layer through the opening
Implementation Method 2
depositing a low-κ layer on the passivated thermal oxide layer through the opening
Data Source
AI summary
Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.