GAA Memory I/O Layout With Doubled Active Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in size of semiconductor elements to enhance price competitiveness of memory devices leads to a single channel effect, and gate-all-around (GAA) transistors require an increase in the number of nanosheets or nanowires, which deteriorates integration density and price competitiveness.
Innovation Solution
An integrated circuit design incorporating a gate-all-around transistor with a specific layout configuration, including multiple active regions, power rails, and signal lines, where the number of active regions is doubled to connect more transistors to each bitcell, enhancing device density and reducing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of nanosheets or nanowires in GAA transistor is increased to address single channel effect, then transistor performance is improved, but integration density deteriorates and device size increases
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to 3D vertical stacking architecture. Multiple GAA transistors are stacked vertically along the channel direction, enabling four transistors to share a single bitcell area. This vertical dimension exploitation resolves the contradiction by improving transistor performance through multiple channels while maintaining high integration density through compact vertical arrangement rather than horizontal expansion.
Solution Approach 2:
The patent implements nested arrangement where multiple GAA transistor channels are nested within a shared bitcell structure. The bitcell contains multiple stacked nanosheet channels that are nested vertically, allowing multiple transistors to occupy the same footprint area. This nesting approach enables enhanced transistor performance through multiple channels while preserving integration density by eliminating the need for separate horizontal space for each transistor.
2Reliability
If the number of nanosheets or nanowires in GAA transistor is increased to address single channel effect, then transistor performance is improved, but device size increases
Solution Approach 1:
The patent moves from 2D planar expansion to 3D vertical stacking. Multiple channels are arranged vertically along the z-axis rather than horizontally in the xy-plane. This dimensional transition allows multiple high-performance channels to be packed into a compact vertical column, improving transistor performance while preventing device size increase in the planar dimensions.
Solution Approach 2:
The patent merges multiple GAA transistor channels into a unified stacked structure within a single bitcell. Instead of separating each transistor into distinct horizontal units, the channels are combined vertically and share common source/drain regions and control structures. This merging reduces the total device footprint while maintaining enhanced performance through the combined effect of multiple channels.
3Reliability
If FinFET structure is used to surround gate three sides of channel, then single channel effect is addressed, but integration density is limited compared to GAA transistor
Solution Approach 1:
The patent advances from 3-sided gate surround (FinFET) to 4-sided gate surround (GAA) by introducing vertical channel orientation. The gate electrode completely encircles the nanosheet channel in all four directions (three sides plus the top surface), providing superior channel control. This full surround geometry enables better integration density because the vertical channel allows tighter packing and more efficient use of the active area compared to the planar FinFET approach.
Solution Approach 2:
The patent segments the channel into multiple discrete nanosheets stacked vertically, each surrounded by its own gate. This segmentation into multiple independent channels within a single vertical stack provides enhanced control over each channel while maintaining high integration density through the compact stacked arrangement. Each segmented channel can be independently controlled, improving reliability while the vertical stacking preserves space.
Data Source
AI summary
An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.