GAA Devices with Isolated Epitaxy for Strain Engineering
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Solution Overview
Problem
In semiconductor device fabrication, incorporating bottom dielectric isolation (BDI) layers in pFET regions is challenging as it leads to loss of strain benefits during epitaxial processing, which is crucial for enhancing hole mobility and performance.
Innovation Solution
The method involves co-integrating BDI layers in nFET regions and non-BDI layers in pFET regions, allowing for enhanced strain in the pFET region by growing pFET layers directly on the substrate, thereby increasing hole mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom dielectric isolation layers are incorporated in pFET regions, then dielectric isolation is improved, but strain benefits are lost during epitaxial processing
Solution Approach 1:
The patent divides the semiconductor device into separate nFET and pFET regions with different epitaxial configurations. The nFET region receives BDI layers for isolation, while the pFET region maintains direct substrate contact for strain benefits. This spatial segmentation allows each region to be optimized independently for its specific functional requirements.
Solution Approach 2:
The patent applies different structural qualities to different regions: BDI layers are applied locally to nFET regions where isolation is critical, while pFET regions maintain direct substrate contact locally to preserve strain-induced hole mobility. This local differentiation resolves the contradiction by allowing each region to have the quality it needs without compromising the other.
2Reliability
If BDI layers are formed on the substrate, then device isolation is improved, but hole mobility in pFET regions deteriorates
Solution Approach 1:
The patent segments the device isolation implementation by applying BDI layers only to nFET regions while leaving pFET regions with direct substrate contact. This segmentation ensures that isolation is provided where needed without interfering with hole mobility in pFET regions.
Solution Approach 2:
Different isolation qualities are applied locally: BDI layers provide strong isolation in nFET regions, while direct substrate contact maintains high hole mobility in pFET regions. This local quality differentiation resolves the contradiction between isolation requirements and mobility requirements in different device regions.
3Speed
If pFET layers are grown directly on the substrate, then hole mobility is improved through strain, but dielectric isolation is reduced
Solution Approach 1:
The patent segments the isolation strategy by using direct substrate contact for pFET regions to maximize hole mobility through strain, while using BDI layers for nFET regions. This segmentation allows each region to be optimized for its primary requirement without compromising overall device isolation.
Solution Approach 2:
Different isolation qualities are applied locally to different regions: pFET regions receive no BDI layers locally to maintain strain and high hole mobility, while nFET regions receive BDI layers locally for strong isolation. This resolves the contradiction by allowing each region to have the isolation quality appropriate for its function.
4Quantity of substance
If stacked nanosheets are implemented, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct regions with different epitaxial requirements. By dividing the device into nFET and pFET regions that can be processed independently, the complexity of fabricating stacked nanosheets is managed through regional specialization rather than uniform complex processing across the entire device.
Solution Approach 2:
Different fabrication approaches are applied locally to different regions of the stacked nanosheet structure. The nFET and pFET regions have different epitaxial configurations (with and without BDI layers respectively), allowing local optimization of fabrication processes while maintaining high device density through the stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved hole mobility and performance in pFET regions while maintaining effective dielectric isolation, reducing the wafer footprint and enhancing overall device performance.
Implementation Method 1
forming a first source-drain epitaxial layer directly on the substrate adjacent to the first FET; and forming a second source-drain epitaxial layer on the substrate adjacent to the second FET
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.