GAA Isolation Layout with Separated CMG and Fin Cuts
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Solution Overview
Problem
The scaling down of Integrated Circuit (IC) technology has increased the complexity of processing and manufacturing, particularly in the formation of Gate-All-Around (GAA) transistors, where existing methods face challenges in reducing damage and parasitic capacitance during the formation of isolation regions.
Innovation Solution
The formation of fully separate Cut-Metal-Gate (CMG) isolation regions, which are not in contact with Continuous Polysilicon on Diffusion edge (CPODE) and Continuous Metal on Diffusion edge (CMODE) isolation regions, thereby reducing damage without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If isolation regions are formed to cut long strips and long gate stacks into shorter portions for GAA transistor fabrication, then manufacturing precision and device structure are improved, but parasitic capacitance increases and damage occurs to the transistor structures
Solution Approach 1:
The patent applies segmentation by dividing the isolation formation process into two separate stages: first forming gate isolation regions to cut gate stacks, then forming fin isolation regions to cut semiconductor regions. This segmentation prevents the formation of continuous isolation regions that would create high parasitic capacitance, while still achieving the necessary isolation function through multiple discrete isolation structures.
Solution Approach 2:
The patent introduces an intermediary approach by using separate gate isolation regions and fin isolation regions instead of a single continuous isolation region. The gate isolation regions act as intermediaries that provide necessary isolation while maintaining lower parasitic capacitance compared to continuous isolation structures, thereby mediating between the need for isolation and the need to minimize parasitic effects.
2Productivity
If scaling down is implemented to increase functional density and production efficiency, then productivity and cost are improved, but processing complexity increases and damage control becomes more difficult
Solution Approach 1:
The patent segments the isolation formation into distinct gate isolation and fin isolation steps, allowing each to be optimized independently for scaled dimensions. This segmentation reduces processing complexity by breaking down the complex isolation formation challenge into manageable, independent processes that can be better controlled at scaled dimensions.
Solution Approach 2:
The patent applies local quality by providing different isolation structures in different locations: gate isolation regions for isolating gate stacks and fin isolation regions for isolating semiconductor regions. This localized approach allows optimization of each isolation type for its specific function and location, managing complexity through specialized local solutions rather than a universal isolation approach.
Data Source
AI summary
A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolations are spaced part from the fin isolation regions.