GAA Isolation Layout With Separated Gate and Fin Cut Regions
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Solution Overview
Problem
The formation of Gate-All-Around (GAA) transistors faces challenges in reducing parasitic capacitance and damage during the process of forming isolation regions, which complicates the manufacturing of advanced ICs.
Innovation Solution
The formation of Cut-Metal-Gate (CMG) and Continuous Polysilicon on Diffusion edge (CPODE) isolation regions is implemented, ensuring they are fully separate and not in contact, thereby reducing damage without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If isolation regions are formed to cut long strips and gate stacks into shorter portions, then the channel layers and gate stacks of GAA transistors can be formed, but parasitic capacitance increases and damage occurs
Solution Approach 1:
The patent applies segmentation by forming separate gate isolation regions and fin isolation regions as distinct, non-contacting structures. The gate isolation regions are positioned between gate stacks while fin isolation regions are positioned between semiconductor regions, creating spatial separation that reduces parasitic capacitance between different isolation structures.
Solution Approach 2:
The patent implements local quality by using different isolation region configurations in different locations: gate isolation regions specifically positioned to isolate gate stacks from each other, and fin isolation regions specifically positioned to isolate semiconductor regions, with each type optimized for its local function to minimize overall parasitic capacitance.
2Productivity
If scaling down process is applied to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent segments the isolation formation process into distinct gate isolation and fin isolation steps with clearly defined spatial relationships. By establishing that gate isolation regions and fin isolation regions are fully separate and non-contacting, the patent simplifies the overall process control while enabling scaled production of complex GAA transistor structures.
Solution Approach 2:
The patent applies preliminary action by forming isolation regions with predetermined spatial separation before final device assembly. The gate isolation regions and fin isolation regions are positioned and configured in advance to ensure they do not contact, preventing parasitic capacitance issues from arising in subsequent processing steps.
Data Source
AI summary
A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolations are spaced part from the fin isolation regions.