GAA Isolation Structure Etching for Uniform Gate Profiles
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Solution Overview
Problem
Existing isolation structures and fabrication techniques for gate-all-around (GAA) transistors face challenges in maintaining device integrity and uniformity during the formation of contacted poly pitch (CPP) due to etching selectivity issues and impurity diffusion, leading to non-uniform gate structure profiles and potential short circuits.
Innovation Solution
A method involving a CPODE process with anisotropic etching is employed to collectively remove the dielectric dummy layer and channel members, ensuring high etching contrast and protecting inner spacers, thereby maintaining device integrity and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form isolation structures in GAA devices, then the isolation structure can be formed, but etching selectivity issues cause non-uniform gate structure profiles and potential short circuits
Solution Approach 1:
The patent introduces an intermediary anisotropic etching process with high etching contrast between the dummy gate material and channel material. This intermediary process acts as a mediator that selectively removes material without causing the selectivity issues present in conventional isotropic etching processes, thereby maintaining profile uniformity and preventing short circuits while forming the isolation structure.
Solution Approach 2:
The patent changes the etching parameters by using anisotropic etching instead of conventional isotropic etching. This parameter change provides high etching contrast and directional control, enabling precise formation of the isolation structure without the selectivity problems that lead to non-uniform profiles and short circuits, thus improving both manufacturing precision and device reliability.
2Productivity
If scaling down continues to increase density for GAA devices, then contacted poly pitch can be reduced, but device integrity and uniformity deteriorate due to etching loss and residue formation
Solution Approach 1:
The patent replaces the conventional mechanical/isotropic etching process with a plasma-based anisotropic etching process. This substitution provides better control over material removal, high etching contrast, and reduced lateral etching, thereby maintaining nanostructure surface uniformity and device integrity even as device density increases through scaling down.
Solution Approach 2:
By changing from isotropic to anisotropic etching parameters, the patent achieves directional material removal with high precision. This parameter change enables continued scaling and increased device density while preventing etching loss and residue formation that would otherwise degrade nanostructure surface uniformity.
3Ease of operation
If CPODE process is used to create isolation structure, then contacted poly pitch can be maintained, but device integrity is compromised due to impurity diffusion
Solution Approach 1:
The patent introduces an intermediary anisotropic etching process with high selectivity as a mediator in the CPODE process flow. This intermediary step enables precise isolation structure formation while minimizing impurity diffusion by providing controlled, directional material removal, thus maintaining both contacted poly pitch control and device integrity simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the uniformity of nanostructure surfaces and gate structures, reducing the risk of short circuits and enhancing the integrity of GAA devices by minimizing etching loss and residue formation.
Implementation Method 1
performing an etching process through the opening to remove the channel members and the dielectric dummy layers in the fin-shaped structure simultaneously
Data Source
AI summary
A method of the present disclosure includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a first region of the fin-shaped structure, selectively removing the sacrificial layers to release the channel layers as channel members, depositing dielectric dummy layers in spaces between the channel members, forming a hard mask layer above the dummy gate stack, patterning the hard mask layer to form an opening directly above the first region of the fin-shaped structure, performing an etching process through the opening to remove the channel members and the dielectric dummy layers in the fin-shaped structure simultaneously, such that a second trench is formed through the dummy gate stack, and depositing an isolation structure in the second trench. The isolation structure divides the dummy gate stack into two segments.