GAA Transistor Isolation Structure for Off-State Leakage Control

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Solution Overview

Problem

In advanced technology nodes of semiconductor fabrication, gate-all-around field-effect transistors face issues with off-state current leakage and anti-punch through implantation regions, particularly in short-channel devices, due to band-to-band tunneling effects at heavily-doped p-n junctions.

Innovation Solution

Incorporation of a p-n junction isolation structure beneath each source/drain portion, with reduced doping concentration in the anti-punch through implantation region, and use of dielectric materials to prevent physical contact and adjust doping levels, thereby minimizing band-to-band tunneling and leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If anti-punch through implantation regions are formed in short-channel devices, then gate control is improved, but band-to-band tunneling effects cause current leakage

Engineering Contradiction:
Improvegate controlVSAvoidcurrent leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating distinct doping concentration zones within the anti-punch through implantation region. A first doping concentration is used in regions adjacent to source/drain portions where high doping is needed for gate control, while a second, lower doping concentration is used in intermediate regions to minimize band-to-band tunneling and current leakage. This spatial variation in doping quality resolves the contradiction between needing strong gate control and avoiding current leakage.

Inventive Principle:
Principle #3Local quality

2Productivity

If heavily-doped p-n junctions are used in gate-all-around transistors, then device performance is improved, but off-state current leakage increases

Engineering Contradiction:
Improvedevice performanceVSAvoidoff-state current leakage
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the doping concentration parameter across different regions of the anti-punch through implantation region. By transitioning from a uniform heavy doping profile to a graded profile with varying doping concentrations, the patent maintains adequate device performance while reducing the severe band-to-band tunneling effects that occur at heavily-doped junctions, thereby reducing off-state current leakage.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If doping concentration in anti-punch through implantation region is reduced, then band-to-band tunneling is minimized, but gate control effectiveness may be compromised

Engineering Contradiction:
Improveband-to-band tunnelingVSAvoidgate control effectiveness
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent resolves this contradiction by applying local quality through spatially differentiated doping concentrations. The higher doping concentration is localized to regions where gate control is most critical (adjacent to source/drain portions), while lower doping concentrations are applied in intermediate regions where band-to-band tunneling is the primary concern. This localized approach maintains gate control effectiveness while minimizing harmful tunneling effects.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces source-to-well and drain-to-well leakage currents, enhancing the performance and reliability of gate-all-around transistors by preventing band-to-band tunneling and maintaining effective gate control.

Implementation Method 1

band-to-band tunneling effects at heavily-doped p-n junctions

Methodology Applied
Scientific EffectBand-to-band tunneling:

Data Source

PatentUS20250331258A1Semiconductor structure with reduced current leakage and method for manufacturing the same
Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250331258A1 patent drawing
  • US20250331258A1 patent drawing
  • US20250331258A1 patent drawing

AI summary

A semiconductor structure includes a first well and a second well which has a conductivity type opposite to that of the first well; a first semiconductor device formed on the first well and including a first channel, two first source/drain portions which have a conductivity type opposite to that of the first well, and at least one first isolation feature including a first doped-semiconductor portion and a first insulating portion, a conductivity type of the first doped-semiconductor portion being the same as that of the first source/drain portions; and a second semiconductor device formed on the second well and including a second channel, two second source/drain portions which have a conductivity type opposite to that of the second well, and at least one second isolation feature including a second insulating portion disposed to separate the second well from a corresponding one of the second source/drain portions.