3D Isolation Structure for GAA Channel Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in scaling down and achieving high performance due to difficulties in reducing off current and improving operation performance, particularly in gate-all-around (GAA) nanowire FET devices.
Innovation Solution
A semiconductor device with an isolation structure comprising vertical and horizontal portions is disposed on a semiconductor substrate to reduce off current and enhance operation performance, where the horizontal portions are connected to the vertical portion, effectively isolating the semiconductor channel layers from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS transistor structure is used, then manufacturing process is simple, but scaling down capability is poor and off current is high
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structure to a three-dimensional structure with vertical portions and horizontal portions extending in multiple directions. This dimensional change enables better channel control and reduced off current while maintaining manufacturing feasibility through extended isolation structures that block leakage paths in three dimensions.
Solution Approach 2:
The isolation structure is divided into multiple segments including vertical portions and multiple horizontal portions that extend in different directions. This segmentation allows the isolation structure to effectively block leakage current paths from multiple directions, reducing off current while maintaining a manageable manufacturing process.
2Productivity
If stereoscopic transistor technology (FinFET, GAA) is adopted, then miniaturization and performance are improved, but further enhancement of operation performance is needed
Solution Approach 1:
The patent applies different structural configurations to different regions of the transistor device. The isolation structure has vertical portions and horizontal portions that extend in specific directions to locally address leakage paths, while the channel layers have specific orientations. This local optimization improves operation performance without requiring complete structural redesign throughout the entire device.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.