GAA Nanostructure Isolation Layout for Leakage Suppression
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors face challenges with leakage current and defects due to high thermal budget processes during shallow trench isolation formation, which affect the electrical performance by increasing off-state leakage and reducing carrier mobilities.
Innovation Solution
A method involving the formation of thin dielectric layers with low thermal budgets, using silicon nitride and physical vapor deposition, and forming bottom isolation layers between source/drain features and the substrate to suppress parasitic transistors and leakage current, while maintaining the integrity of channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high thermal budget processes are used for shallow trench isolation formation, then isolation effectiveness is improved, but off-state leakage current increases and carrier mobility decreases
Solution Approach 1:
The patent changes the thermal budget parameter from high to low during shallow trench isolation formation. By using low thermal budget processes, the patent avoids the harmful effects of high temperature processing while still achieving effective isolation. This parameter change resolves the contradiction by decoupling isolation effectiveness from thermal budget requirements.
Solution Approach 2:
The patent introduces consumable sacrificial layers (silicon germanium layers) that are deliberately designed to be temporary and removable. These sacrificial layers serve their purpose during fabrication and are then selectively removed to release the channel layers, enabling the gate structure to wrap around them. This approach allows complex 3D structures to be formed using simpler, less thermally intensive processes.
2Reliability
If high thermal budget processes are used for shallow trench isolation formation, then isolation effectiveness is improved, but carrier mobility decreases
Solution Approach 1:
The patent changes the thermal budget parameter from high to low during isolation formation. By maintaining low processing temperatures, the patent preserves the electrical properties and carrier mobility of the semiconductor materials while still achieving effective isolation between devices.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that enable the formation of wrapped gate structures without requiring high temperature processes. These intermediary layers facilitate the self-aligned formation of complex 3D structures through low-temperature deposition and selective removal, preserving material quality.
3Ease of manufacture
If conventional fabrication processes are used for GAA transistors, then manufacturing simplicity is maintained, but defects increase due to thermal impact
Solution Approach 1:
The patent segments the fabrication process into distinct stages with sacrificial layers serving as temporary structures for each stage. The channel layers are formed as separate entities using low-temperature processes, then released and wrapped with gate structures. This segmentation allows complex 3D structures to be built from simpler components without high-temperature processing.
Solution Approach 2:
The patent uses consumable sacrificial layers that are intentionally designed to be temporary and removable. These layers enable complex structure formation during fabrication and are then selectively removed, allowing the final device to be formed without the defects associated with high-temperature processing of the complete structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the off-state control and overall electrical performance of GAA transistors by reducing leakage current and defects, enhancing carrier mobility without significant thermal impact.
Implementation Method 1
forming thin dielectric layers with low thermal budgets, using silicon nitride and physical vapor deposition
Data Source
AI summary
Semiconductor structures and methods are provided. In an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.