GAA Transistor Isolation Height Tuning for Multi-Voltage ICs
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Solution Overview
Problem
Existing semiconductor technologies face challenges in designing integrated circuits with varying voltage and current requirements, as most transistors have similar intrinsic features like metal gate and source/drain structures, leading to increased design complexity.
Innovation Solution
The development of gate-all-around (GAA) field-effect-transistor (FET) devices with different dimensions for metal gate and source/drain structures, allowing for the formation of transistors that can operate under different voltage and current levels by adjusting isolation structure heights between groups of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors have similar intrinsic features like metal gate and source/drain structures, then manufacturing process is simplified, but design complexity increases when varying voltage and current requirements are needed
Solution Approach 1:
The patent applies local quality by forming isolation structures with different heights in different regions of the semiconductor device. Specifically, first isolation structures have a first height while second isolation structures have a second height greater than the first height, allowing different transistor regions to have tailored characteristics for specific voltage and current requirements while using a unified manufacturing process
2Adaptability or versatility
If isolation structure heights are adjusted between groups of transistors, then transistors can operate at different voltage and current levels, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming all isolation structures with different heights during the same deposition process step. The isolation structures are formed concurrently with the metal gate structure, where the deposition process automatically creates different heights based on the underlying topography, eliminating the need for subsequent separate height-adjustment steps and reducing precision requirements
Data Source
AI summary
A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.