Gate-All-Around Transistor Isolation Stack for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing three-dimensional stacked complementary transistor exhibits high parasitic capacitance between gate stack structures, leading to poor alternating current characteristics due to the presence of a middle dielectric isolation layer and differences in metal gate materials, which complicates manufacturing and affects yield.
Innovation Solution
The semiconductor device incorporates alternately stacked first and second dielectric isolation layers with different dielectric constants, positioning the gate stack structures at the periphery of these layers to reduce parasitic capacitance, and includes gate spacers and inner spacers to enhance manufacturing efficiency and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a middle dielectric isolation layer is used between stacked transistors, then electrical isolation is improved, but parasitic capacitance between gate stack structures increases
Solution Approach 1:
The single middle dielectric isolation layer is segmented into multiple alternating dielectric isolation layers with different dielectric constants. This segmentation allows the structure to provide electrical isolation while reducing parasitic capacitance by using layers with lower dielectric constants in critical regions between gate stack structures.
Solution Approach 2:
Different regions of the dielectric isolation structure use materials with different dielectric constants optimized for local requirements. Regions closer to gate stack structures use materials with lower dielectric constants to minimize parasitic capacitance, while other regions use materials with higher dielectric constants for effective electrical isolation.
2Reliability
If different metal gate materials are used in stacked transistors, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate stack structures are segmented into different material regions corresponding to different transistor types (N-type and P-type). This allows each region to be optimized with appropriate metal gate materials while using a unified multi-layer dielectric isolation structure to simplify the overall manufacturing process.
3Productivity
If three-dimensional stacked complementary transistor structure is adopted, then integration density is improved, but parasitic capacitance between adjacent transistors increases
Solution Approach 1:
The vertical stack is segmented into alternating layers of different dielectric materials, creating multiple isolation zones between adjacent transistors. This segmentation reduces the parasitic capacitance coupling between N-type and P-type transistors while maintaining the high integration density of the three-dimensional stacked structure.
Solution Approach 2:
The dielectric isolation structure uses composite materials with different dielectric constants arranged in alternating layers. This composite structure provides optimized electrical isolation and reduced parasitic capacitance, enabling high-density three-dimensional stacking while maintaining signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance, improves alternating current characteristics, and enhances the manufacturing yield and electrical reliability of the semiconductor device.
Implementation Method 1
first dielectric isolation layers and second dielectric isolation layers alternately stacked between a channel region included in the first gate-all-around transistor and a channel region included in the second gate-all-around transistor
Implementation Method 2
a parasitic capacitance between a gate stack structure included in an upper-layer gate-all-around transistor and a gate stack structure included in a lower-layer gate-all-around transistor is large
Data Source
AI summary
Provided is a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulation layer, and first and second dielectric isolation layers. The insulation layer is arranged between a source/drain region of the first gate-all-around transistor and a source/drain region of the second gate-all-around transistor. The first dielectric isolation layers and the second dielectric isolation layers are alternately stacked between a channel region of the first gate-all-around transistor and a channel region of the second gate-all-around transistor. A gate stack structure of the first gate-all-around transistor and/or a gate stack structure of the second gate-all-around transistor is located at a periphery of alternately stacked first and second dielectric isolation layers. Film layers located at bottom and top layers in alternately stacked first and second dielectric isolation layers are both first dielectric isolation layer.