Gate-All-Around Semiconductor Device With Variable Isolation Layer Thickness
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Solution Overview
Problem
Conventional semiconductor devices with gate-all-around structures face challenges in controlling channel current and suppressing leakage currents due to the short channel effect, limiting their electrical performance.
Innovation Solution
The method involves forming semiconductor devices with specific thickness variations in isolation layers and gate structures to create different threshold voltages across device regions, allowing for improved control over channel resistance and performance by varying the thickness of isolation layers and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around structure is used to surround the device channel, then control over channel current is improved, but manufacturing precision becomes more difficult due to the complex multi-layer isolation structure required
Solution Approach 1:
The patent divides the isolation structure into multiple discrete layers (first isolation layer, second isolation layer, third isolation layer) with different thicknesses and material compositions. Each layer serves a specific function: the first isolation layer provides base isolation, the second isolation layer with smaller thickness provides selective isolation in the second device region, and the third isolation layer fills gaps and provides final isolation. This segmentation allows precise control of threshold voltages in different device regions while maintaining manufacturability through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The patent implements different isolation layer thicknesses and materials in different device regions. The second isolation layer has a thickness smaller than the first isolation layer, creating different threshold voltages for devices in the first device region versus the second device region. This local variation in isolation structure properties allows simultaneous optimization of devices with different electrical requirements on the same substrate, improving overall device performance while using conventional fabrication techniques.
2Productivity
If the device size is reduced to continue Moore's Law, then integration density is improved, but short channel effect increases causing leakage current issues
Solution Approach 1:
The patent implements a nested isolation structure where the first isolation layer, second isolation layer, and third isolation layer are stacked vertically to form a multi-layer nested configuration. The gate structure surrounds the channel from multiple sides, and the isolation layers are nested within and around the gate structure. This nested arrangement provides enhanced electrical isolation and threshold voltage control in scaled devices, effectively suppressing leakage currents while maintaining small device footprint for high integration density.
3Adaptability or versatility
If different threshold voltages are required for different device regions, then device versatility is improved, but device complexity increases due to multiple isolation layers with different thicknesses
Solution Approach 1:
The patent varies the thickness parameter of isolation layers across different device regions to achieve different threshold voltages. The first isolation layer has a first thickness, the second isolation layer has a second thickness smaller than the first thickness, and the third isolation layer has a third thickness. By changing this thickness parameter in a controlled manner during fabrication, the patent creates devices with different electrical characteristics (different threshold voltages) in different regions, enabling versatile device designs for different applications while using the same basic fabrication process flow.
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first device region and a second device region; forming a first doped layer on the semiconductor substrate; forming a first fin layer on the first doped layer in the first device region; forming a second fin layer on the first doped layer in the second device region; forming a first isolation layer on the first doped layer in the first device region and covering sidewall surfaces of the first fin layer; forming a second isolation layer on the second doped layer in the second device region and covering portions of sidewall surfaces of the second fin layer and with a thickness smaller than a thickness of the first isolation layer; and forming a first gate structure on the first isolation layer and a second gate structure on the second isolation layer.