Non-Uniform Isolation Trenches for GAA Leakage Blocking
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Solution Overview
Problem
The formation of Gate-All-Around (GAA) transistors requires efficient methods to create isolation regions that effectively prevent leakage currents while maintaining the structural integrity and performance of the transistors, as the complexity of manufacturing these advanced ICs increases with smaller geometries.
Innovation Solution
The formation of isolation regions with non-uniform depths, where the outer isolation regions are deeper than the inner regions, utilizing controlled etching processes to enhance barrier effectiveness against leakage currents, and employing specific etching gases and plasma conditions to achieve this non-uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform depth isolation regions are formed, then the manufacturing process is simple, but the barrier effectiveness against leakage currents is insufficient
Solution Approach 1:
The patent applies asymmetry by forming isolation regions with non-uniform depths where outer isolation regions extend deeper than inner isolation regions. This asymmetric depth configuration creates enhanced barrier effectiveness against leakage currents at the edges of the semiconductor device, while maintaining a simpler overall structure compared to uniformly deep isolation regions throughout the entire device area.
Solution Approach 2:
The patent implements local quality by varying the depth of isolation regions based on their position within the device structure. Outer isolation regions are formed deeper to provide enhanced leakage current blocking at critical edge locations, while inner isolation regions maintain shallower depths sufficient for their local requirements, optimizing the overall isolation performance without unnecessary complexity.
2Reliability
If outer isolation regions are formed deeper than inner regions, then leakage current blocking is enhanced, but the etching process complexity increases
Solution Approach 1:
The patent employs periodic action through a multi-step etching process that alternates between etching inner isolation regions and outer isolation regions. The process involves forming inner isolation regions to a first depth, then etching outer isolation regions to a greater second depth, and finally performing a planarization step. This periodic etching approach enables precise control over the non-uniform depth profile while managing process complexity through systematic, repeatable steps.
Solution Approach 2:
The patent applies preliminary action by first forming the inner isolation regions to a shallower depth before etching the outer isolation regions to the greater depth. This sequential approach allows the etching process to establish a baseline isolation structure first, then selectively extend the depth at outer regions where enhanced leakage blocking is required, simplifying the overall manufacturing sequence.
3Reliability
If non-uniform depth isolation regions are formed, then transistor performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements feedback through a planarization step performed after etching the outer isolation regions to a greater depth. This planarization process removes excess material and creates a uniform top surface, providing feedback control that ensures the non-uniform depth profile is achieved with precise depth control. The planarization step compensates for variations in the etching process, maintaining manufacturing precision despite the complex non-uniform depth requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the barrier effectiveness against leakage currents, improving the performance and reliability of GAA transistors by effectively isolating semiconductor regions, thereby supporting the complex manufacturing needs of advanced ICs.
Implementation Method 1
employing specific etching gases and plasma conditions to achieve this non-uniformity
Data Source
AI summary
A method includes forming a plurality of semiconductor structures over a semiconductor substrate, forming a dummy gate stack on top surfaces and sidewalls of the plurality of semiconductor structures, forming gate spacers on sidewalls of the dummy gate stack, and etching a first portion of the dummy gate stack to form a through-gate trench in the dummy gate stack. The dummy gate stack includes a second portion and a third portion on opposing sides of the first portion. Through the through-gate trench, the plurality of semiconductor structures are etched to form a trench group underlying and connected to the through-gate trench. The trench group includes two outmost trenches, and at least one inner trench between the two outmost trenches. The two outmost trenches are deeper than the at least one inner trench.