GAA Logic Cell Back-Side Power Routing for Higher Circuit Density
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, gate-all-around (GAA) transistors face challenges with VDD and VSS power routing, which consumes excessive routing resources and impacts cell scaling and performance.
Innovation Solution
The implementation of a semiconductor device structure with a back-side interconnect structure for VDD and VSS voltage lines, reducing routing loading in the front-side interconnection and improving circuit density by arranging these voltage lines in the back-side interconnect structure, thereby decreasing metal conductor resistance-capacitance (RC) performance and power IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If VDD and VSS power routing is implemented in the front-side interconnect structure, then power delivery is achieved, but routing resources are excessively consumed and cell scaling is impacted
Solution Approach 1:
The patent moves power routing from the front-side interconnect structure to the back-side interconnect structure, utilizing the third dimension (vertical stacking) to resolve the routing resource conflict. This dimensional transition allows power lines to be routed on the back side of the device, freeing up front-side routing resources for signal connections and enabling continued cell scaling.
2Reliability
If VDD and VSS power routing is implemented in the front-side interconnect structure, then power delivery is achieved, but cell scaling and performance are impacted
Solution Approach 1:
By relocating power routing to the back-side interconnect structure, the patent enables reduced cell footprint in the planar dimensions. The vertical separation of power and signal routing allows for more compact cell designs while maintaining adequate power delivery paths.
3Reliability
If more routing resources are allocated to VDD and VSS power routing, then power delivery is improved, but circuit density is reduced
Solution Approach 1:
The back-side interconnect structure provides dedicated space for power routing without consuming routing resources that would otherwise be available for signal connections. This spatial separation enables higher circuit density while maintaining robust power delivery paths.
Data Source
AI summary
Semiconductor devices are provided. A logic cell includes P-type GAA nanosheet transistor and N-type GAA nanosheet transistor. Each of the P-type and N-type GAA nanosheet transistors has two channel members vertically stacked. A back-side interconnect structure includes first and second back-side contacts, a VDD line formed in a back-side metal layer and coupled to a source feature of the P-type GAA nanosheet transistor through the first back-side contact, and a VSS line formed in the back-side metal layer and coupled to a source feature of the N-type GAA nanosheet transistor through the second back-side contact. A front-side interconnect structure includes first and second front-side contacts, and a metal line coupled to a drain feature of the P-type GAA nanosheet transistor through the first front-side contact or coupled to a drain feature of the N-type GAA nanosheet transistor through the second front-side contact.