GAA Nanosheet Logic With MOL Resistors for Capacitance-Heat Tradeoffs
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Solution Overview
Problem
Prior middle-of-the-line (MOL) resistors in semiconductor technology face a trade-off between low capacitance and low self-heating, with those optimized for low capacitance exhibiting high self-heating and vice versa, limiting their performance in high-speed and high-DC current applications.
Innovation Solution
A semiconductor structure is developed that co-integrates nanosheet logic devices with precision MOL resistors, optimizing different regions for low capacitance and low self-heating by using distinct gate structures and source/drain configurations, including the placement of metal resistors above gate structures and direct contact with semiconductor sub-fins for heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If MOL resistors are optimized for low capacitance, then capacitance is reduced, but self-heating increases
Solution Approach 1:
The patent segments the semiconductor substrate into distinct device regions: logic device regions with full nanosheet stacks and source/drain regions, and resistor device regions with gate structures but without source/drain regions. This segmentation allows MOL resistors to be formed in regions optimized for low capacitance by excluding the high-capacitance source/drain structures, while the logic regions maintain both low capacitance and low self-heating through the presence of source/drain heat dissipation paths.
Solution Approach 2:
The patent applies local quality by creating different structural configurations in different regions of the semiconductor substrate. Resistor device regions have gate structures wrapped around nanosheets without underlying source/drain regions, providing low capacitance characteristics. Logic device regions have both gate structures and source/drain regions, providing both low capacitance and low self-heating through thermal dissipation. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific function.
2Temperature
If MOL resistors are optimized for low self-heating, then self-heating is reduced, but capacitance increases
Solution Approach 1:
The patent segments the semiconductor substrate into distinct device regions: logic device regions with full nanosheet stacks and source/drain regions, and resistor device regions with gate structures but without source/drain regions. This segmentation allows MOL resistors to be formed in regions optimized for low capacitance by excluding the high-capacitance source/drain structures, while the logic regions maintain both low capacitance and low self-heating through the presence of source/drain heat dissipation paths.
Solution Approach 2:
The patent applies local quality by creating different structural configurations in different regions of the semiconductor substrate. Resistor device regions have gate structures wrapped around nanosheets without underlying source/drain regions, providing low capacitance characteristics. Logic device regions have both gate structures and source/drain regions, providing both low capacitance and low self-heating through thermal dissipation. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific function.
3Temperature
If source/drain regions are added to nanosheet devices, then self-heating is reduced through heat dissipation, but device complexity increases
Solution Approach 1:
The patent segments the semiconductor substrate into distinct device regions: logic device regions with full nanosheet stacks and source/drain regions, and resistor device regions with gate structures but without source/drain regions. This segmentation allows MOL resistors to be formed in regions optimized for low capacitance by excluding the high-capacitance source/drain structures, while the logic regions maintain both low capacitance and low self-heating through the presence of source/drain heat dissipation paths.
Solution Approach 2:
The patent applies universality by using the same gate structure fabrication process for both logic devices and MOL resistors. The gate structures serve dual purposes: as functional transistors in logic device regions and as resistor elements in resistor device regions. This multi-functionality reduces overall device complexity by eliminating the need for separate resistor fabrication processes while still providing the heat dissipation benefits of source/drain regions where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and self-heating, enhancing the performance of MOL resistors in high-speed and high-DC current applications by optimizing specific regions for low capacitance and self-heating characteristics.
Implementation Method 1
the source/drain region present in the second resistor device region drains heat generated by the second metal resistor into the semiconductor substrate that is connected to the semiconductor sub-fin
Data Source
AI summary
A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.