3D Gate-All-Around Memory Structure for Computing-in-Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing Von Neumann architecture-based processing systems face limitations in handling large amounts of data due to the separation of data processing and storage units, leading to restricted computing speeds and data transfer rates.
Innovation Solution
A three-dimensional memory structure with a gate-all-around (GAA) configuration, comprising multiple channel bodies, gate structures, and side plugs, which allows for high-capacity and high-speed data processing by enabling computing-in-memory operations without the need for data transfer between processing and storage units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data processing unit and data storage unit are separated (Von Neumann architecture), then device structure is simple and ease of manufacture is improved, but data transfer rate is limited and computing speed is restricted
Solution Approach 1:
The patent merges the data processing unit and data storage unit into a unified memory structure where transistors are formed within the memory cell structure itself. The channel bodies, gate structures, and source/drain regions are integrated such that processing and storage occur in the same physical location, eliminating the need for data transfer between separate units and thereby improving computing speed while maintaining manufacturing simplicity through a unified fabrication process.
2Device complexity
If data processing unit and data storage unit are separated (Von Neumann architecture), then device complexity is reduced, but data transfer rate becomes the bottleneck
Solution Approach 1:
The patent combines processing and storage functions within the same memory cell structure, where transistors are formed using channel bodies that pass through gate structures. This integration eliminates data transfer between separate processing and storage units, removing the speed bottleneck while maintaining manageable device complexity through a unified structure that uses standard semiconductor fabrication processes.
3Productivity
If computing-in-memory operations are enabled, then computing speed and capacity are improved, but device structure becomes more complex
Solution Approach 1:
The patent segments the memory structure into multiple channel bodies, each with associated gate structures and source/drain regions. This segmentation allows multiple computing operations to occur in parallel within different channel bodies, improving overall computing speed and capacity. The segmented structure maintains manageable complexity by using repeating units that can be fabricated using standard processes, with each segment independently contributing to the total computing capability.
Solution Approach 2:
The patent introduces a vertical dimension by forming channel bodies that extend through multiple gate structures stacked along a first direction, with side plugs extending in a second direction perpendicular to the gate structures. This three-dimensional arrangement enables computing-in-memory operations with improved density and speed while maintaining manufacturability through vertical integration rather than lateral expansion, effectively adding a spatial dimension to the computing architecture.
Data Source
AI summary
A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.