GAA Memory I/O Layout for Higher Bitcell Integration Density
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Solution Overview
Problem
The reduction in size of semiconductor elements, such as GAA transistors, leads to increased integration density, which deteriorates the integration density of semiconductor devices and weakens price competitiveness.
Innovation Solution
An integrated circuit design incorporating a gate-all-around (GAA) transistor with specific arrangements of active regions, power rails, and signal lines, allowing for a higher number of transistors connected to each bitcell without increasing the device size, thereby enhancing integration density and reducing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of nanosheets or nanowires of the GAA transistor is increased to enhance performance, then the performance of the memory device is improved, but the size of the memory device increases and the integration density deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional GAA transistor structures where the gate completely surrounds the channel in the vertical dimension. This dimensional change allows for better electrostatic control and higher performance without proportionally increasing the planar footprint, thereby maintaining integration density while improving device performance
Solution Approach 2:
The gate structure is nested around the channel region in a complete surround configuration, with the gate wrapping around the channel from all sides. This nested arrangement maximizes the control of the channel by the gate while minimizing the space required, allowing high performance with compact dimensions that preserve integration density
2Ease of manufacture
If the size of semiconductor elements is reduced to enhance price competitiveness, then manufacturing cost is reduced, but the integration density of semiconductor devices deteriorates
Solution Approach 1:
The patent employs precise control of critical dimensions including the channel width, gate thickness, and nanosheet/nanowire diameter to optimize device performance. By carefully selecting and controlling these parameters, the invention achieves high performance and high integration density simultaneously, making the device both competitive in cost and dense in integration
3Reliability
If the number of fins in FinFET is increased to adjust performance and size, then the performance and size are optimized, but the device complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete nanosheets or nanowires stacked vertically, with each segment providing an independent conduction path. This segmentation allows for scalable performance adjustment by simply adding or removing segments without increasing lateral complexity, as the stacked structure maintains a regular, repeating pattern that is easier to manufacture than complex fin arrangements
Data Source
AI summary
An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.