GAA Memory Transistor Layout for Leakage and Read Window Control
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Solution Overview
Problem
The increasing complexity and scaling down of semiconductor integrated circuits (ICs) lead to higher power dissipation, which is challenging to address effectively using existing technologies.
Innovation Solution
The implementation of gate-all-around (GAA) devices with improved isolation structures to reduce current leakage, combined with flexible gate contact placement strategies within memory bit-cells and peripheral devices, such as NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional density is increased and geometry size is decreased through scaling down, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The patent implements gate-all-around (GAA) structures where the gate electrode completely surrounds the channel region in three dimensions, transitioning from traditional planar 2D gate control to 3D wraparound control. This dimensional change enables superior electrical control over the channel while maintaining scaled-down geometry, thereby reducing power dissipation without sacrificing production efficiency
Solution Approach 2:
The patent employs high-k dielectric materials combined with metal gate electrodes to form composite gate structures. This composite approach enables better electrical control with lower leakage currents, addressing the power dissipation issue that arises from scaling down while maintaining the benefits of increased functional density
2Reliability
If gate-all-around structures are implemented to reduce current leakage, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct components including gate electrodes, gate dielectric layers, and channel regions, with each segment serving a specific function. This segmentation allows for optimized control of threshold voltage while managing structural complexity through modular design
Solution Approach 2:
By implementing the gate structure in three dimensions with complete wraparound control, the patent achieves superior threshold voltage control without requiring proportional increases in lateral complexity. The vertical dimension provides additional control leverage
3Reliability
If flexible gate contact placement strategies are used within memory bit-cells, then read window is expanded, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs flexible gate contact placement strategies that can be dynamically adjusted within memory bit-cells, allowing optimization of read window based on specific operational requirements. This dynamic adaptability enables improved reliability while managing manufacturing precision through design flexibility
Data Source
AI summary
A method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.