GAA Memory Transistor Structure With SiGe Dopant Diffusion Barriers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit (IC) devices continue to downscale, there is a need for improved operation speed and accuracy, as well as enhanced performance and reliability in field effect transistors with a gate-all-around structure, particularly in preventing N-type dopant diffusion from source/drain regions to channel layers.
Innovation Solution
The semiconductor device incorporates a Si1−xGex anti-diffusion layer with x≠0, strategically located between the source/drain region and the channel layers, to prevent N-type dopant diffusion. This layer is discontinuously extended in the vertical direction, ensuring electrical connection while maintaining the integrity of the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N-type dopant is introduced into source/drain regions to improve electrical conductivity, then conductivity is improved, but dopant diffuses into channel layers causing threshold voltage shifts and reliability degradation
Solution Approach 1:
A Si1-xGex anti-diffusion layer is introduced as an intermediary barrier between the N-type doped source/drain region and the channel layer. This layer selectively blocks N-type dopant diffusion into the channel while maintaining electrical connectivity through its semiconductor properties, thus preventing threshold voltage shifts and reliability degradation without compromising source/drain conductivity
Solution Approach 2:
The anti-diffusion layer is formed using Si1-xGex composite material, which combines silicon and germanium in specific ratios. This composite structure provides both the diffusion barrier properties needed to prevent dopant migration and the electrical conductivity required to maintain device operation, resolving the contradiction between blocking dopant and maintaining electrical function
2Productivity
If device size is reduced to achieve higher integration density, then integration density is improved, but dopant diffusion control becomes more difficult and reliability decreases
Solution Approach 1:
The anti-diffusion layer is segmented into multiple discrete layers positioned at different vertical levels between the source/drain region and channel layers. This segmentation approach provides enhanced dopant blocking capability at each interface while maintaining the overall compact structure needed for high integration density, effectively preventing diffusion even in scaled-down devices
Solution Approach 2:
The anti-diffusion structure extends into the vertical dimension with multiple layers at different heights, creating a three-dimensional barrier configuration. This vertical dimensionality provides superior dopant blocking compared to single-planar structures, enabling reliable dopant control in highly scaled devices without sacrificing integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the Si1−xGex anti-diffusion layers effectively enhances the reliability of the semiconductor device by preventing dopant diffusion, thereby maintaining high operation accuracy and performance, even as device scaling continues.
Implementation Method 1
The plurality of anti-diffusion layers are located only between the source/drain region and the plurality of channel layers to discontinuously extend in the vertical direction
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes: a substrate; an active region extending in a first direction on the substrate; a plurality of channel layers stacked on the active region and spaced apart from each other in a vertical direction perpendicular to the first direction; a gate structure extending on the active region in a second direction perpendicular to the first direction and the vertical direction, and surrounding the plurality of channel layers; a source/drain region provided on at least one side of the gate structure on the active region and electrically connected to the plurality of channel layers; and a plurality of anti-diffusion layers stacked and spaced apart from each other in the vertical direction and extending in the second direction.