GAA Transistor Mesa Profile for Leakage Current Suppression
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistors in semiconductor devices faces challenges with strong leakage current due to the gate structure engaging the top portion of the semiconductor substrate, which affects device performance.
Innovation Solution
A modified mesa profile is created with a concave sidewall structure to suppress leakage current by increasing the resistance of the current path through the mesa, achieved by patterning and etching processes that form a tapered and then concave profile on the sidewalls of the mesa.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure extends around the bottommost channel layer to provide gate-all-around control, then gate control is improved and sub-threshold leakage is reduced, but strong leakage current occurs under the stacked channel layers due to engagement with the top portion of the semiconductor substrate
Solution Approach 1:
The mesa structure is segmented into multiple regions with different sidewall profiles: a first region with a first sidewall profile and a second region with a second sidewall profile. This segmentation allows different portions of the mesa to have different electrical characteristics, where one region controls leakage while another maintains mechanical support.
Solution Approach 2:
Different regions of the mesa are given different sidewall profiles tailored to their specific functions. The first region has a first sidewall profile optimized for leakage suppression, while the second region has a second sidewall profile optimized for mechanical strength. This local differentiation resolves the contradiction between leakage reduction and structural integrity.
2Object-generated harmful factors
If the mesa structure is modified to suppress leakage current through increased resistance, then leakage current is reduced, but mechanical strength of the mesa may be compromised
Solution Approach 1:
The mesa is divided into multiple regions with different sidewall profiles. The first region uses a profile optimized for electrical isolation (lower mechanical strength) while the second region uses a profile optimized for mechanical support (higher strength). This segmentation allows each region to be optimized for its primary function without compromising the other.
Solution Approach 2:
The mesa structure implements local quality differentiation where different regions have different sidewall profiles. The first region has a profile that increases electrical resistance to suppress leakage, while the second region has a profile that maintains mechanical strength. This localized optimization resolves the contradiction between electrical and mechanical requirements.
Data Source
AI summary
A semiconductor device includes a substrate, nanostructures disposed over a mesa protruding from the substrate, a gate structure wrapping at least one of the nanostructures and interfacing with opposing sidewalls of the mesa, an epitaxial source/drain feature abutting the nanostructures, and an isolation feature deposited on the opposing sidewalls of the mesa and sidewalls of the epitaxial source/drain feature. The opposing sidewalls of the mesa bend inwardly towards a center of the mesa such that a narrowest width of the mesa is between 0.5 and 0.9 of a width of a top surface of the mesa. The width of the top surface of the mesa equals a width of the nanostructures.