Gate-All-Around Metal Gate Layout for Tight N-P Boundaries
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits faces challenges with the conventional subtractive metal gate process, particularly in achieving tight N-P boundary control and high transistor density due to issues with isotropic wet etching, which results in wide N-P boundaries and undercutting, degrading device performance.
Innovation Solution
The implementation of an additive metal gate process, which involves depositing a high-temperature hard mask, patterning, and using a wet etch to protect the work function metal layer, thereby bypassing the difficulties of isotropic wet etching and enabling tight N-P boundary control and high transistor density in gate-all-around architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional subtractive metal gate process with isotropic wet etching is used, then manufacturing simplicity is maintained, but N-P boundary control deteriorates and transistor density decreases
Solution Approach 1:
The patent inverts the conventional subtractive metal gate approach by using an additive metal gate process. Instead of depositing metal gates across the entire substrate and then etching away portions, the invention directly deposits work function metals only in the desired gate regions using atomic layer deposition (ALD) with in-situ patterning. This inversion eliminates the isotropic wet etching step that causes boundary widening and undercutting, thereby achieving precise N-P boundary control while maintaining manufacturing feasibility through a streamlined process.
Solution Approach 2:
The patent applies preliminary action by performing in-situ patterning and work function metal deposition before subsequent processing steps. The high-temperature hard mask is deposited and patterned first, creating a template that guides the precise deposition of work function metals in the exact desired locations. This preliminary patterning action ensures that metal gates are formed only where needed, preventing any boundary control issues that would arise from later etching operations.
2Productivity
If isotropic wet etching is used to remove metal gates, then ease of manufacture is maintained, but transistor density and performance deteriorate due to wide N-P boundaries and undercutting
Solution Approach 1:
The patent extracts the problematic isotropic wet etching step from the manufacturing process entirely. By using an additive approach where work function metals are deposited only in desired gate regions through ALD with in-situ patterning, the invention removes the need for subsequent metal gate removal etching. This extraction eliminates the source of boundary widening and undercutting, enabling high transistor density while maintaining manufacturing simplicity through the direct deposition method.
Solution Approach 2:
The patent substitutes the mechanical/chemical etching process with a deposition-based approach. Instead of using wet etching chemistry to define gate regions, the invention uses physical vapor deposition (ALD) with in-situ patterning to directly form metal gates in the desired locations. This substitution replaces a process that inherently causes boundary control issues with one that provides precise spatial control from the outset, improving transistor density without sacrificing ease of manufacture.
3Quantity of substance
If feature size is scaled down to increase transistor density, then capacity increases, but lithographic process constraints and N-P boundary control worsen
Solution Approach 1:
The patent transitions from a planar, two-dimensional patterning approach to a three-dimensional deposition approach with vertical control. By using atomic layer deposition (ALD) with in-situ patterning, the invention achieves precise control over metal gate formation in the vertical dimension while maintaining horizontal precision. This dimensional shift allows sub-10nm scaling with excellent N-P boundary control, as the ALD process inherently provides atomic-layer precision and the in-situ patterning ensures accurate lateral placement, enabling high transistor density without boundary control degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additive metal gate process effectively addresses the limitations of the subtractive metal gate method by maintaining precise N-P boundary control and enhancing transistor density, leading to improved device performance and manufacturing efficiency.
Implementation Method 1
using a wet etch to protect the work function metal layer
Data Source
AI summary
Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.