3D Gate-All-Around MOSFET Channel Structure for Scaled Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring a three-dimensional field effect transistor structure with a gate-all-around configuration, including a gate electrode that surrounds channel patterns, and a specific arrangement of source/drain and channel patterns to enhance connectivity and spacing, along with a gate insulating pattern and spacers to improve reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for smaller pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction (third direction) perpendicular to the substrate, enabling increased effective channel area without expanding the lateral footprint. This dimensional transition allows continued device scaling while maintaining operational properties by providing additional conduction pathways in the vertical dimension.
Solution Approach 2:
The gate electrode structure completely surrounds each channel pattern in a nested configuration, with the gate wrapping around the channel from all sides including top, bottom, and lateral surfaces. This gate-all-around structure provides enhanced electrostatic control over the channel, improving device reliability and operational characteristics while enabling smaller device dimensions through superior field effect control.
2Area of moving object
If MOSFETs are scaled down, then pattern size is reduced, but electrical characteristics deteriorate
Solution Approach 1:
Multiple channel patterns are stacked vertically in the third direction to create a three-dimensional structure. This stacking increases the total effective channel area and improves electrical characteristics such as drive current without increasing the lateral pattern size. The vertical stacking enables continued miniaturization while maintaining or enhancing electrical performance through increased channel capacity.
Solution Approach 2:
The gate electrode is configured to completely surround each channel pattern, with gate portions extending above and below the channel in the vertical direction and laterally around the channel sides. This nested gate-all-around structure provides superior electrostatic control, improving threshold voltage modulation and reducing short-channel effects, thereby enhancing electrical characteristics in scaled-down devices.
3Reliability
If gate electrode surrounds channel patterns (gate-all-around configuration), then electrostatic control is improved, but device complexity increases
Solution Approach 1:
The gate electrode is divided into multiple discrete gate portions, with each gate portion individually surrounding a specific channel pattern. The semiconductor structure is segmented into multiple stacked channels, allowing independent formation and control of each channel-gate unit. This segmentation simplifies the fabrication process compared to forming a single continuous gate around all channels, while still achieving gate-all-around electrostatic control for each individual channel.
Solution Approach 2:
The gate electrode extends in the vertical third direction to surround the channel patterns from top, bottom, and lateral surfaces. By utilizing the vertical dimension for gate wrapping, the structure achieves complete electrostatic control without requiring complex lateral interconnections or additional control elements, thereby managing device complexity while maximizing electrostatic effectiveness.
Data Source
AI summary
A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.