Gate-All-Around Nanoribbon Layout for Transistor Size Variability
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Solution Overview
Problem
Integrated circuit fabrication faces challenges in scaling down memory and logic cells due to the lack of variability in transistor designs, particularly in gate-all-around and fork-sheet architectures, which makes it difficult to adjust performance between transistors on the same die.
Innovation Solution
The solution involves forming non-planar semiconductor devices, such as gate-all-around transistors, with varying numbers of nanoribbons across different regions of the substrate. This is achieved by using epitaxial growth to increase the thickness of substrate regions, allowing for devices with different numbers of nanoribbons to be formed without the need for depopulation processes that can damage other structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate-all-around and fork-sheet architectures are used to maximize semiconductor surface utilization, then device density and surface efficiency are improved, but design variability and performance adjustability between transistors deteriorate
Solution Approach 1:
The patent applies local quality by varying the number of nanoribbons in different device regions while maintaining the same gate-all-around architecture. Specifically, first devices are formed with a first number of nanoribbons and second devices are formed with a second number of nanoribbons, allowing each device type to have optimized performance characteristics tailored to its specific function while utilizing the semiconductor surface efficiently
Solution Approach 2:
The patent segments the semiconductor device structure into multiple nanoribbons that can be selectively formed in different quantities. By dividing the channel structure into discrete nanoribbon units, the design can adjust the effective channel width by including or excluding specific nanoribbons, thereby achieving performance variability without changing the fundamental architecture
2Adaptability or versatility
If depopulation processes are used to adjust the number of nanoribbons in devices, then device size variability is improved, but damage to other exposed structures occurs
Solution Approach 1:
The patent applies preliminary action by forming the selective nanoribbon structure through controlled epitaxial growth before any depopulation processes. The different numbers of nanoribbons are established during the growth phase itself, so that when gate trenches are later formed, all structures are already in their final configurations, eliminating the need for damaging depopulation processes
Solution Approach 2:
Instead of starting with a uniform structure and removing nanoribbons (depopulation), the patent inverts the approach by selectively growing nanoribbons only where needed. This growth-based approach achieves the same device size variability without the harmful effects of etching and removal processes
3Productivity
If transistors are scaled down in size to increase integration density, then circuit capacity is improved, but manufacturing difficulty and performance adjustment capability deteriorate
Solution Approach 1:
The patent applies universality by using a single gate-all-around fabrication process that can produce devices with different numbers of nanoribbons. The same epitaxial growth and gating steps serve multiple functions, creating both high-density integration and performance variability without requiring separate manufacturing lines or additional process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the modulation of device size by adjusting the number of nanoribbons, allowing for the formation of transistors with varying effective sizes on the same substrate, thereby addressing the challenge of performance adjustment between transistors and enhancing the efficiency of integrated circuit fabrication.
Implementation Method 1
This is achieved by using epitaxial growth to increase the thickness of substrate regions, allowing for devices with different numbers of nanoribbons to be formed
Data Source
AI summary
Techniques are provided herein to form non-planar semiconductor devices (e.g., gate-all-around or forksheet devices) on the same substrate that have a different total number of semiconductor bodies (e.g., nanoribbons) in the channel region. Any number of semiconductor devices each includes one or more semiconductor bodies extending in a first direction, and a gate structure extending in a second direction over each of the semiconductor bodies. Source or drain regions are formed at ends of the one or more semiconductor bodies of each device. Different regions of the substrate have different relative thicknesses, such that devices formed across the different regions have a different number of semiconductor bodies while the gate structures of the devices have a substantially coplanar top surface. In this way, different devices on the substrate can have any number of semiconductor bodies. Topmost semiconductor bodies of each such device may be collinear or coplanar with each other.