GAA Nanosheet Gate Structure for Bottom Channel Control
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Solution Overview
Problem
As semiconductor technology advances to sub-10-15 nm nodes, gate-all-around (GAA) FETs face challenges in achieving full depletion and minimizing short-channel effects due to the incomplete gate control over the channel region, particularly the bottom side, which affects performance and reliability.
Innovation Solution
The manufacturing process involves forming vertically stacked multiple channels with nanosheets or nanowires, using alternately stacked semiconductor layers, forming fin structures, and creating a sacrificial gate structure with a specific etching and spacer formation to ensure complete gate dielectric and electrode coverage around the channel regions, thereby enhancing control and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a Fin FET gate structure is used where the gate electrode is adjacent to three side surfaces of the channel region, then the manufacturing process is simpler, but the gate control over the channel is insufficient due to the bottom part being far from the gate electrode
Solution Approach 1:
The patent transitions from a planar gate structure (Fin FET with gate on three sides) to a three-dimensional gate-all-around structure where the gate electrode completely surrounds the channel region including the bottom surface. This dimensional change enables full gate control over all channel surfaces, resolving the gate control insufficiency while maintaining manufacturing feasibility through advanced lithography and etching techniques
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes to achieve higher device density, then the device density increases, but short-channel effects worsen and full depletion becomes difficult to achieve
Solution Approach 1:
The gate-all-around structure wraps the gate electrode completely around the channel region in three dimensions, providing superior electrostatic control at scaled dimensions. This dimensional approach enables full depletion of the channel even at sub 10-15 nm nodes, effectively suppressing short-channel effects while maintaining high device density
Solution Approach 2:
The gate electrode is nested around the channel region with the gate dielectric layer interposed between them, creating a concentric structure where the gate completely surrounds the channel. This nested configuration ensures that all surfaces of the channel are under close gate control, achieving full depletion and minimizing short-channel effects at scaled dimensions
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.