GAA Nanosheet Channel Structure for Lower Resistance and S/D Isolation
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Solution Overview
Problem
Multi-gate transistors face challenges such as higher channel resistance due to longer channel lengths and lighter dopant concentrations, which affect manufacturing efficiency and device performance, particularly in nanosheet FETs and GAA devices.
Innovation Solution
The solution involves intentionally enlarging the width of the bottom nanostructure to reduce channel resistance and improve epitaxial growth of source/drain regions, while maintaining a narrower top nanostructure to prevent S/D merging, using various manufacturing methods like photolithography and self-aligned processes to pattern gate-all-around transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to reduce short-channel effects, then device control is improved, but channel resistance increases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FinFET, GAA nanosheets). This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), providing superior electrostatic control without requiring increased channel length, thus maintaining low channel resistance while improving device control.
Solution Approach 2:
The gate structure completely surrounds the channel region in a nested configuration (gate-all-around). The gate wraps around the channel from all directions, creating a nested structure where the channel is enclosed within the gate's electrical field. This provides maximum control over the channel with minimal resistance, as the gate controls the channel from all sides simultaneously.
2Object-affected harmful factors
If the bottom nanostructure width is enlarged to reduce channel resistance, then channel conductivity is improved, but source/drain merging may occur
Solution Approach 1:
The patent applies different width characteristics to different regions of the nanostructure. The bottom nanostructure has an enlarged width to reduce channel resistance and improve conductivity, while the top nanostructure maintains a narrower width to prevent source/drain merging. This local differentiation of geometric properties allows each region to optimize its function independently.
Solution Approach 2:
The nanostructure exhibits asymmetric geometry where the bottom width differs from the top width. This asymmetry is intentionally designed to create a wider base for better electrical conduction while maintaining a narrower top section for reliable source/drain isolation. The asymmetric profile optimizes both electrical performance and structural integrity.
3Reliability
If multi-gate structures are implemented to improve device control, then transistor performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct sequential stages: forming the semiconductor stack with alternating layers, patterning to create the desired geometry, selective removal of sacrificial layers, and gate formation. Each stage is independently optimized and controlled, making the complex multi-gate structure manufacturable through systematic breakdown of the fabrication sequence.
Solution Approach 2:
Sacrificial layers are pre-formed between the semiconductor layers during stack fabrication. These preliminary sacrificial structures guide subsequent patterning and self-aligned processes. By preparing these guiding structures in advance, the complex multi-gate geometry can be accurately formed without requiring highly complex real-time manufacturing control.
Data Source
AI summary
Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor structures, a source/drain (S/D) region, and a gate stack. The substrate includes an active region extending along a first direction. The semiconductor structures are stacked on the active region. The S/D region abuts the plurality of semiconductor structures. The gate stack wraps the semiconductor structures and extends along a second direction different from the first direction. A bottommost semiconductor structure of the semiconductor structures has a width in the second direction greater than a width of a topmost semiconductor structure of the semiconductor structures in the second direction.