GAA Nanosheet Sacrificial Layers for Channel Release Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits while managing increasing complexity and power dissipation, requiring innovative manufacturing processes to maintain efficiency and reduce costs.
Innovation Solution
The use of gate all around (GAA) transistor structures with multi-layer sacrificial layers and epitaxial stacks, where the sacrificial layers have different semiconductor compositions to facilitate etching and oxidation selectivity, allowing for the formation of nanosheet channels and high-k/metal gate structures, optimizing epitaxy and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The channel is divided into multiple nanosheets (first channel nanosheet, second channel nanosheet, etc.) stacked vertically. This segmentation allows the device to maintain smaller effective channel dimensions for high density while distributing the current path across multiple segments, reducing power dissipation through increased surface area for heat dissipation and improved electrical characteristics.
Solution Approach 2:
The invention transitions from planar 2D channel structures to three-dimensional vertically-stacked nanosheet channels. By stacking multiple channel nanosheets in the vertical dimension, the device achieves higher functional density without further reducing the lateral geometry size, thereby maintaining power dissipation at acceptable levels while increasing production efficiency.
2Loss of energy
If multi-gate devices are used to reduce power dissipation, then power consumption is lowered, but device complexity increases
Solution Approach 1:
The gate structure wraps around all sides of each channel nanosheet, providing multi-gate control that simultaneously achieves multiple functions: (1) reduced power dissipation through improved channel control, (2) enhanced carrier injection efficiency, and (3) improved heat dissipation. This universal gate design reduces device complexity by consolidating multiple control functions into a single integrated structure.
Solution Approach 2:
The device employs composite material structures including alternating layers of semiconductor materials (e.g., SiGe/Si/SiGe) to form the channel nanosheets. These composite structures enable the nanosheets to be selectively released and controlled while maintaining mechanical integrity, reducing the complexity of handling and fabricating individual nanosheets compared to using purely rigid or purely flexible materials.
3Productivity
If scaling down is pursued to increase functional density, then manufacturing efficiency is improved, but structural isolation becomes more difficult
Solution Approach 1:
Sacrificial layers (e.g., SiGe layers) are introduced as intermediary structures during fabrication. These sacrificial layers are deposited between the channel nanosheets, providing temporary structural support and isolation that simplifies the fabrication process. The sacrificial layers are later selectively removed to release and suspend the nanosheets, achieving the desired structural isolation without complicating the manufacturing process.
Solution Approach 2:
The channel nanosheets are formed and stacked in a preliminary integrated structure before final release and isolation. This preliminary action allows the nanosheets to be fabricated and positioned with precise control while still supported by the sacrificial layers, simplifying the subsequent isolation steps compared to attempting to isolate each nanosheet individually during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient channel release and improved gate length control, reducing structural variability and protecting source/drain epitaxial structures, thereby enhancing the manufacturing process for advanced semiconductor devices.
Implementation Method 1
forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of sacrificial layers and a plurality of channel layers alternately arranged over the semiconductor substrate
Implementation Method 2
employing selective etching to create uniform inner spacers for structural isolation
Data Source
AI summary
A method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of sacrificial layers and a plurality of channel layers alternately arranged over the semiconductor substrate, and each of the sacrificial layers is a multi-layer film comprising a bottom epitaxial layer, a middle epitaxial layer over the bottom epitaxial layer, and a top epitaxial layer over the middle epitaxial layer, wherein the middle epitaxial layer has a lower germanium concentration than the bottom and top epitaxial layers; laterally recessing the sacrificial layers to form sidewall recesses alternating with the channel layers; forming inner spacers in the sidewall recesses; forming source/drain epitaxial structures on opposite sides of the channel layers.